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Clock Multiplier?
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6079smith



Joined: Jan 18, 2007
Posts: 95
Location: Mark of the Dane
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PostPosted: Fri Sep 21, 2007 6:00 am    Post subject: Clock Multiplier?
Subject description: ...do they exist?
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Just curious about this... is there a circuit that works the opposite way to a clock divider? You know, takes a clock signal and outputs it multiplied by 2, 4, 8, whatever, so another clock-based circuit will run at that new tempo? Or perhaps it's called something else? Or am I thinking through my hat?
Any ideas?
Thanks,
Andrew
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factus10



Joined: Jun 20, 2007
Posts: 158
Location: Buffalo, NY

PostPosted: Fri Sep 21, 2007 7:04 am    Post subject: Reply with quote  Mark this post and the followings unread

Here's a design that appeared in EDN using a delay line:
http://www.edn.com/index.asp?layout=article&articleid=CA45865
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yusynth



Joined: Nov 24, 2005
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PostPosted: Fri Sep 21, 2007 7:10 am    Post subject: Reply with quote  Mark this post and the followings unread

Yes this is possible it's what does a frequency synthesizer (NOT A SOUND SYNTHESIZER ! ). It is based on a phase locked loop circuit.
For instance it could use a 4046 circuit. The 4046 contains a basic VCO that runs at a high frequency, the signal (square) goes through dividers and is compared through a XOR gate to the signal to be "freq multiplied", the phase/frequency differences generate pulses at the output of the XOR gate. The width of these pulses is proportional to the difference in phase. These pulses are then integrated (lowpass filter by a basic RC cell) and the resulting voltage is fed back to the CV input of the 4046 that will shift in frequency to minimize the difference in frequency.
Using different values for the divider stage let's you set the frequency multiplication coefficient, say if you use a dive by two counter then the frequency is doubled and so on.

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factus10



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PostPosted: Fri Sep 21, 2007 7:18 am    Post subject: Reply with quote  Mark this post and the followings unread

What he said.

The author of the delay line method mentions that "it takes a long time for [a 4046 PLL] circuit to reach a stable output frequency, and the frequency-drift compensation has a complex design."

I'm not sure what "a long time" is but I'm guessing hundreds of ns, which is probably an issue in microprocessor clock designs.
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6079smith



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PostPosted: Fri Sep 21, 2007 7:32 am    Post subject: Reply with quote  Mark this post and the followings unread

Thanks for the suggestions. Googling something like "clock multiplier" just gives a wealth of completely useless information. Although with the right keywords...
I presume this (by Scott Gravenhorst) could be adapted? It seems to be more or less what Yves suggests. I guess without the LFO input, mixer output etc.

Hey, I might even get this to work. Again, thanks for the responses.
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yusynth



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PostPosted: Fri Sep 21, 2007 7:38 am    Post subject: Reply with quote  Mark this post and the followings unread

6079smith wrote:
T
I presume this (by Scott Gravenhorst) could be adapted? It seems to be more or less what Yves suggests. I guess without the LFO input, mixer output etc.


Yes that's it !

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