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 Forum index » DIY Hardware and Software » Developers' Corner
Fixed vs floating point DSP math
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dewdrop_world



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PostPosted: Thu Sep 20, 2007 7:40 am    Post subject: Fixed vs floating point DSP math Reply with quote  Mark this post and the followings unread

Starting a few posts down on this page, you can find a fascinating discussion of the merits and issues of floating-point vs fixed-point math for DSP.

http://www.electro-music.com/forum/post-139880.html

Well worth a read for the technically curious.

James

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JovianPyx



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PostPosted: Sat Feb 02, 2008 10:46 am    Post subject: Reply with quote  Mark this post and the followings unread

Interesting stuff. Because an FPGA can do DSP tasks, I made a decision to take the FPGA route instead of the dedicated DSP IC route. Mainly because the FPGA can do the DSP stuff as well as the more perfunctory tasks such as an embedded MIDI receiver/controller.

In the FPGA environment, fixed point arithmetic isn't as confining as it is in fixed width dedicated processor systems. Hypothetically, if you're using a device that natively supports N bits fixed point, and you need 2N bits, you're stuck with using extra clocks to get the job done. In fact, if all you need is N+1 bits, you're still stuck with the extra clocks. With an FPGA, you can just make your arithmetic words wider and calculate in one clock. Floating point can also be implemented in an FPGA, but you are then required to use an FP IP core or make your own. So far, using an FPGA for synthesizers, I've needed only fixed point. Some things need wider words, so I make those wide, otherwise I make them only as wide as they need to be. You think differently when using fixed point because you don't have a magical mantissa fixer-upper working for you. Nevertheless, you can make rich featured, very good sounding synth hardware using only fixed point math.

Where the FPGA hits a similar problem of (potentially) extra clocks, is when using fixed width dedicated hardware multipliers and needing more precision than they singly provide, but even then, if the system clock is slow enough, multipliers can be cascaded to get double width performance without necessarily adding extra clock cycles.

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