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 Forum index » DIY Hardware and Software » Klee sequencer
Pimping Your Klee
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a.b.o.z.



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PostPosted: Fri Apr 11, 2008 11:26 am    Post subject: Pimping Your Klee
Subject description: Modifying the Klee
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can one make klee to run in reverse?
is it posible? modification?

Edit: This topic was split from Electro-Music Klee Sequencer Build and Applications Thread

-Scott
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PostPosted: Fri Apr 11, 2008 11:47 am    Post subject: Reply with quote  Mark this post and the followings unread

Quote:
can one make klee to run in reverse?
is it posible? modification?


The CD4034 shift registers can accept parallel data bi-directionally but the the data will only shift one way. The shifting can not be made to go bidirectional. No DIRECTION pin exists. Very Happy You would have to add a fair bit of circuitry to make it shift bi-directionally. I would imagine maybe some sort of MUX arrangement using [16] 2:1 mux elements. The arrangement would be:

MUX BIT16, BIT1
MUX BIT15, BIT2
MUX BIT14, BIT3
.
.
MUX BIT1, BIT16

The MUX outputs would have to take the place of the CD4034 outputs and the MUX inputs would use the CD4034 outputs as shown above .... There most likely would be an easier way? I am just blurting things out fast .... Wink

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PostPosted: Fri Apr 11, 2008 3:11 pm    Post subject: Reply with quote  Mark this post and the followings unread

Righto. As I've mentioned before, the Klee does provide the right hooks for expansion, should you want to do this kind of stuff. And you may, Ivan, seeing as how it would make things spin in the opposite direction which would be, if anything, visually stunning on your Klee.

As Bill mentions, it would take some multiplexing, plus you would need to clock the load rather than shifting the register.

There may be easier ways, but the way I would tackle it would be to connect the pattern switches through CD4053s. On the other inputs of the CD4053s I would connect the next highest step's output. So, for example, output 3 would connect back to pattern input 2, output four would connect back to input 3, and so on and so forth.

The forward/reverse switch would then have the task of (when set to reverse) switching the pattern switches out of the circuit and instead connect the bit outputs back to the inputs AND it would have to switch the clock impulse from the serial clock to the load circuit. Every clock pulse would then shift the bits backward with each pulse.

'Course, that would take six 4053s. I imagine some other device (such as CD4019 maybe) would be reduced to four. There may be an even more economical way of doing it. It would take a sub-board that would be an intermediary between the pattern switch and data line connectors that could do all the processing, plus +V and ground connections.

It'd be a fun project.

Cheerio,
Scott

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PostPosted: Sat Apr 12, 2008 1:37 am    Post subject: Reply with quote  Mark this post and the followings unread

Yeah,
I was gonna say that! Laughing
Pretty simple really.

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PostPosted: Sat Apr 12, 2008 7:35 am    Post subject: Reply with quote  Mark this post and the followings unread

Is it possible to add a second clock, allowing the two halves of the Klee to advance at different rates?
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PostPosted: Sat Apr 12, 2008 8:14 am    Post subject: Reply with quote  Mark this post and the followings unread

Yeah, Andy, it was such an intriguing idea, I couldn't help but sketching it last night in Express Schematic. If the idea worked, it could be done as a fairly simple PCB. That is, if it worked.

"Ben Hur" came on just as I started it, and it was right about at the chariot race that I started wondering about that aspect of it. I used CD4019s for the switch (mainly because I have a buttload of unused CD4019s here). The uncertainty of it in my mind is the parallel load aspect of it. This is the problem: are the two signals that generate the asynchronous parallel load fast enough to ensure that it "steps backward" only one step? As long as async is high, the registers are going to push the contents of the A side of the CD4034 over to the B side. It may be fine, but it would definitely need proven.

There are other things that would have to be taken into account as well - how to handle the load functions while its in reverse mode (not to mention switching the clock signal to load instead of clock), etc. Some stuff would need disabled while it was happening.

Now, some (not all) CD4034 datasheets (and my beloved RCA CMOS bible) have an example circuit of a left/right application that involves the use of four CD4034s, though two of them could be eliminated I think. I more or less ignored that app when I first started working on the Klee because I figured two of those buggers were enough to slap into a unit, and things were varied and complicated as it was. That was before I had an inkling of Krunkoid PCBs.

My design went totally the opposite direction - so opposite, in fact, it's pretty well painted into a corner for preventing the method shown in the datasheet. Which is too bad, because it would be a seamless operation to switch directions on the fly, and add some functionality without increasing the front panel load at all or by too much. In fact, I though it would be doable without drilling a single hole - just make the gatebus1 load three position, with the extra position being "reverse". But the trace cutting and debauchery required to do it is beyond the pale (my goal was that the original boards would not be harmed by Exacto).

To make a long post not go too much longer, this morning as I was wondering around with my customary tousled hair and torn underwear blearily drinking my coffee ((there's a mental image for you), it struck me. Nearly everything that is needed to pull it off is present at the CD4034 sockets. Jump those pads to a new board and create the ultimate Super electro-music Klee. In fact, I think it would only require one seven wire harness to jump form these sockets to the new Special K board. Not only would it add a reverse function, but the opportunity to optionally add functionality I regret not implementing would be right there as well. It could certainly all be implemented without a single scrape of razor against trace.

The things I think of would be synchronous external load, an integral clock, full reverse functionality, the ability to clock and load the registers separately (more register autonomy), and maybe even optional individual gate out per stage. Some of that would require a different panel, but two of them (the synchronous external load and reverse functionality) could be put into existing panels.

Mebbe a new thread - tricking out your Klee - would be in order?

Cheerio,
Scott

PS: In the windage it took to post this, looks like Bananaplug has posted.

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PostPosted: Sat Apr 12, 2008 8:19 am    Post subject: Reply with quote  Mark this post and the followings unread

Bananaplug,

Not without some serious modification (or at least enough modification to keep it from doing weird stuff in 16X1 mode). In order to keep a 16X1 pattern going smoothly, the register clocks need to be locked together. But, I hear you - clocking both registers at different rates in 8X2 would be tremendous.

It's certainly possible taking the route discussed in my previous post above.

Cheerio,
Scott

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PostPosted: Sat Apr 12, 2008 4:53 pm    Post subject: Reply with quote  Mark this post and the followings unread

Scott Stites wrote:
I have a buttload of unused CD4019s


That sounds really uncomfortable.
Maybe it explains the torn underwear! Laughing

No, seriously, I get where you're coming from. Didn't I suggest we start a "Pimp ya Klee" thread a while ago?

Adding more functionality sounds like fun. We just have to make sure the mods work so we can guarantee that it's worth "getting jiggy wid ya box"
Show me the schems you've come up with, and we can look at maybe knocking up a test bed. You, Tom and I all have a Klee now, (quite a few other people do/will have one too now) so testing should be fairly straight forward.

An extra panel, once justified, would be fairly easy to implement with a set of D-type connectors and ribbon cable. As long as people have used fairly decent sockets for the 4034s, those could be used to plug straight into the board if you think that is the best spot to tap. Otherwise, replacing the sockets with headers is not out of the question.

BTW I've done a lot of de-soldering (sucker) and replacing parts lately on my ASM2 board (which is almost identical quality to the Klee) and I haven't lifted a pad or lost a plate through yet. As long as it's done carefully, it's not as scary as you might think.

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PostPosted: Sat Apr 12, 2008 5:05 pm    Post subject: Reply with quote  Mark this post and the followings unread

CD4019's ain't so bad - try shoving a CD4034 in the undies and see how your day changes.....

I've battered you with a number of schematics - check yer inbox. It's a basic layout of a quite enhanced encoder section designed to implement a number of functions, including stepping forward and reverse. This is all done with an eye towards retrofitting existing panels and replacing two position switches with three position switches in order to do a number of ghastley things.

For separate panels, I've long thought of a half zillion things that could be implemented in a "helper" module, which wouldn't necessarily be Klee-centric, either.

Cheerio,
Scott

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PostPosted: Sat Apr 12, 2008 6:10 pm    Post subject: Reply with quote  Mark this post and the followings unread

Do you think you should break this thread over to a new "pimping yer Klee" one before we go much further?
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PostPosted: Sun Apr 13, 2008 7:48 am    Post subject: Reply with quote  Mark this post and the followings unread

Consider it geshplit.

electro-music Janitorial Staff

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PostPosted: Sun Apr 13, 2008 4:20 pm    Post subject: Reply with quote  Mark this post and the followings unread

Here's a first pass at putting in a board to convert the electro-music Klee to the electro-music Uber Klee.....

It would require no cutting of traces. The CD4034s would be removed from the digital board and put on this board, probably the same would go for the CD4053 switch (there is Uber Switching on this board). So, the 4034s depicted here would not be additional ICs, and one of the CD4053s would replace the CD4053 on the digital board.

There are a lot of things this part would do, chief among them would be fully incorporated reverse stepping and synchronous load. Also, it allows new things to be done with the Invert function (it would now be applicable to either or both registers) and the random function (same thing - more versatile across both registers).

Reverse functionality would be as easy as the flip of a switch - the Klee would just reverse direction seamlessly. If it was in the random mode at the time, it would start feeding the random signal to the opposite end. Externally or manually loading a pattern would work the same in either direction.

Synchronous Load is something I've wanted for a long time; even before I stuck a fork in the current design and called it done.

Simply put, right now the Klee loads the patterns asynchronously. That means, as soon as you push that Load button or send an external load signal, the Klee instantly loads the current pattern. There are a number of advantages to this, but the disadvantage is if you're Kleeing along and you start riffing with different patterns. You have to be very good at hitting that load button at the right time.

With synchronous load, when you press the load button or send an external load signal, the Klee will *not* load the pattern right away. It will wait for the next clock pulse to come along and then load. That way, a different pattern will always hit right on the beat and you won't have to worry with "barging in" mid beat. Sync/Async load is switchable with this design - you can have it when you want it and not when you don't.

This stuff coud be added to existing panels with some ingenious switch changeouts. New panels could take advantage in new ways.

I haven't yet turned my attention to giving the registers more clock autonomy (using a different clock for each register), but this approach totally allows it. 8X2 would definitely be good; 16X1 would get weird, but I guess it's a question of if it's a good weird or a bad weird. If it's a bad weird, it can be arranged to automatically assert only one clock in 16X1 mode.

I should mention that only the sync/async and forward/reverse control logic is shown. I don't have the control of the 4053s illustrated yet.

More later - I gotta do my taxes; right now I'm trying to figure out if I should declare those pennies on my eyes in advance.....

Cheerios,
Scott

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PostPosted: Sun Apr 13, 2008 8:47 pm    Post subject: Reply with quote  Mark this post and the followings unread

Phooey - I had the inverter/RC on Q instead of /Q in the original drawing. So, here it is corrected. Plus an explanation of the Sync/Async load function (I'll get to forward/reverse next):


Sync/Async Control

"Sync" is switch signal intended to be controlled with a toggle switch. When "Sync" is high, the pattern bits are loaded synchronously, when "Sync" is low, the pattern bits are loaded asynchronously.

"PSA" and "R_Async" are two signals provided by the original Klee, and are used for loading pattern bits asynchronously. In the original operation, when a pattern load is initiated, "PSA" pulses high, which put the CD4034s in parallel mode. While "PSA" is still high, "R Async" pulses high, putting the CD4034s in asynchronous mode, and whatever bit pattern was present at the inputs would automatically be jammed into the registers. Then "R Async" would go low, putting the CD4034s back in synchronous mode. Then "PSA" would go low, putting the CD4034s in the serial mode of operation.

The proposed left shift operation (reverse) relies upon the CD4034s to be clocked in the parallel mode. This naturally provides an opportunity to synchronously load patterns. However, right shift operation must resort to some extra effort to pull things off. For either mode, asynchronous pattern load operation must be preserved as well.

Lets consider what needs to happen for a synchronous load operation: the signal to load must be received and "remembered" until a rising clock pulse causes the actual pattern load to happen. In order to do that, a simple memory device in the form of a CD4013 is used to "remember" the command to load a bit pattern the next time the clock signal transistions high.

When the command to load the pattern is received, either remotely through the External Load Jack or the Manual Load Switch, "PSA" pulses high. This signal is connected to the "Set" input of the bottom half of the CD4013, which causes the Q signal of that section to go high and stay high until it is clocked low; this is the "memory" element. This high signal is NANDed with the "Sync" signal, which is set high when Synchronous Mode is desired. Because of the two high signals on its input, the NAND gate output goes low. This high-to-low transition is inverted by a section of a CD40106 to a low-to-high transition, which is ORed with PSA. The OR gate is there to allow PSA to have an effect for Asynchronous Mode, but in this case, is really not contributing anything, because the high input originating at the flipflop remains high much longer than PSA will. The end result is the output of this OR gate is again ORed with the "L/R" control signal.

The "L/R" control signal is high when left shift is desired, and low when right shift is desired. When "L/R" is high, it puts the CD4034s in parallel mode, which is required for left shift operation. If the Klee is already in left shift mode, then this whole business with the flipflop is really unnecessary. However, consider that the Klee is in right shift mode - L/R will be low, and we need something to put the CD4034s in parallel mode. The high output of the flipflop in this case will force the CD4034s into parallel operation. At this point, the B side inputs of the CD4034 are now acting as parallel data inputs.

But the data on the CD4034 B inputs is not shoved into the shift registers just yet - they are still in the synchronous mode. The signal to place them in the asynchronous mode, "R Async", has been disabled by the "Sync" signal. Notice "R Async" is NANDed with the inverted "Sync" signal - "R Async" will go high, but because it is NANDed with the inverted "Sync" signal, which is a low, the output of that NAND gate will remain high. The output of the NAND gate is inverted, so it is low. This low signal "P/S" is applied to the parallel/serial control input of the CD4034s, which keeps them in synchronous mode.

Because the CD4034s are in synchronous mode, the data present at the B inputs of the CD4034s will not load until the clock signal "RClock" next transitions high. Now, we have to be sure to load the right data.

The left shift mode of operation relies on the CD4034s loading the positionally staggered A side output bits, so, in this mode, the CD4019s are normally directing this data to the CD4034 B inputs. For right shift operation, there is no issue - the pattern switch data is already directed to the CD4034 inputs. But, for left shift pattern loading, the CD4019s must be "told" to stop sending the staggered A data and, for the time being, send send the pattern switch bit data instead.

The high data originating from the flipflop takes care of this. It is ORed with the inverted L/R data (which is used to select the 4019 output during non-pattern load operation). In the case of left shift operation, this signal is low, and is just doing us no good at the moment. In right shift mode, this inverted data would be high, and we would have no worries. Fortunately, the flipflop high "memory" element forces the output of this OR gate high, which causes "LoadPat" to go high and "LoadData" to go low. This set of conditions tells the CD4019s to send the pattern switch data to the CD4034 B inputs, so our bases are covered here.

So, now all we have to do is wait for a clock pulse to come along to actually load the pattern bits. Sooner or later, the "RClock" pulse arrives. Its rising edge clocks the top section of the CD4013 flipflop. The low portion "Q" output is holding this top section's data input high, so its Q output clocks high and its /Q output drops low. /Q dropping low generates a positive pulse out of the RC coupled inverter connected to it. This high pulse resets the top section and it clocks the lower section, causing our remembered "high" to drop low. This has the effect of arming the CD4013 to look for the next desired manual or external load command.

All of this protocol was designed for this ends: slightly before our memory element drops low, telling the CD4034s to go back to serial operation (if the Klee is in right shift mode), the same "RClock" signal has clocked the pattern switch data into the CD4034s - mission accomplished!

Asynchronous load is more straightforward. In the asynchronous load mode, the "Sync" signal is low. Notice that the flipflop still goes through its gyrations, but now it is simply ignored. The high output of the flipflop is NANDed with "Sync", and, because "Sync" is low, the memory signal does not make it past this first test. However, now that "Sync" is low, "R Async" now causes the output of its NAND gate to go low, and that output (A/S) is inverted high so the CD4034s will now be in asynchronous mode as long as it is ever-so-briefly high.

"PSA" also is allowed through downstream - it is first ORed with the non-existent "memory" signal, but because it is ORed, it passes on through to the output of the OR gate. Next, it is ORed with the "L/R" signal. Again, if the left shift mode is on ("L/R" is high), PSA is rather irrelevant at this point - the CD4034s are already in the parallel mode. However, in right shift mode, PSA will force the CD4034s to the parallel input mode.

The output of this OR gate is also ORed with the inverted "L/R" signal. This ensures that "LoadPat" is brought high and "LoadData" is brought low, telling the CD4019s to present the pattern switch data to the CD4034 B data inputs. So, "PSA" goes high, ensuring the CD4034s are in the parallel input mode and the correct data is presented to their parallel inputs, and "R Async" follows, throwing the CD4034s into the asynchronous mode, causing them to load the presented pattern switch data. Afterwards, as usual, "R Async" goes low, placing the CD4034s into synchronous mode, and, PSA goes low, placing the CD4034s in serial mode if right shift is active, and parallel mode if left shift is active.


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PostPosted: Mon Apr 14, 2008 12:14 pm    Post subject: Reply with quote  Mark this post and the followings unread

Thanks for "snappin' it off" Mr Scott! Very Happy
I'm not sure about these things. Embarassed

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PostPosted: Tue May 06, 2008 10:34 am    Post subject:
Subject description: stealing this thread...
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would it be possible to have the triggers of each bus to be the same regardless of merging the gates or not?

ie, for bus 1, connecting c19 to pin 6 instead of 4 of U12?

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PostPosted: Wed May 07, 2008 11:02 am    Post subject: Reply with quote  Mark this post and the followings unread

I don't think that would work - there are a couple of things preventing it.

The first thing is the polarity - the signal coming from gate bus 1 (pin 6 of U12) goes high and would be inverted by U11.

The second thing is that the signal coming from Gate Bus 1 is not differentiated between two consecutively high stages. In other words, if stage 1 causes gate bus 1 to go high, then stage 2 causes gate bus 1 to go high, gate bus 1 will never actually go low between those two steps. That's the purpose served by delayed clock - the state of the bus is ANDed with that clock pulse, and when the clock pulse goes low, the ANDed signal goes low. Merge simply disables ANDing the clock pulse with the gate bus, so the gate output stays high as long as there is a high switched to the gate bus. The triggers are derived from the transition of the gate signal swinging from low to high.

Other sequencers address this by providing a blanking pulse - the Klee instead relies on comparing to the clock - that's why the on-time of the gates are directly tied to the on-time of the clock when the bus is not merged.

Your suggestion could be done, but it would take some extra gates.

Cheerio,
Scott

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PostPosted: Thu May 08, 2008 2:53 am    Post subject: Reply with quote  Mark this post and the followings unread

Hmm, so its a bit more complicated eh...

What I'm after is something like this:
Posted Image, might have been reduced in size. Click Image to view fullscreen.
Gate merged.

I guess I have to solved externally.
Right now I have no use connecting both bus 1-3 gates and triggers to the same EG... I alwaly use one or the other.

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PostPosted: Thu May 08, 2008 10:24 am    Post subject: Reply with quote  Mark this post and the followings unread

My EGs will respond in three different ways if I have trigger only, gate only, or gate and trigger, respectively.

Concerning gate or trigger only, as you know, the effect a gate bus output will have on an EG in merged mode will be different. Three merged gates will provide a note (or series of notes sharing the same envelope) with the length of the three clock pulses with a gate. Three merged gates will produce 1 triggered envelope the length of which is determined by the release or decay.

What I like to do is cross the gate output of one gate bus with the trigger output of the other. Then one can have a gated EG that is re-triggered by the other gate bus trigger output. Even the master trigger out combined with a merged (or unmerged) gate output from a different bus provides some nice variation.

A spiff module, I suppose, would be a simple AND gate with a trigger output. Run the merged gate into one input and the clock into the other - as long as the gate stayed high, it would generate one trigger output per clock pulse.

Cheerio,
Scott

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PostPosted: Thu May 08, 2008 1:13 pm    Post subject: Reply with quote  Mark this post and the followings unread

Yes, I thought about 'cross-patching' the gate and trigger chords after posting , but I have not tried it yet. I better do that before modifying. Smile
Thanks for the answers. Very Happy

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PostPosted: Thu May 15, 2008 3:44 pm    Post subject: Reply with quote  Mark this post and the followings unread

Hi Scott,

Great add-on for the klee. I am laying out the circuit, I am confused about the control lines for the 4053's . Do I have to jumper a 4053 to the new board and where do I get the control lines for all the switches?

Many thanks.

R.
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PostPosted: Sat May 17, 2008 7:23 am    Post subject: Reply with quote  Mark this post and the followings unread

Hey Ringer,

Yipes! I haven't tested any of this, so you're in uncharted waters. That, and the rev 2 had a mistake (I'm attaching the corrected version here). Rev 2 left out a connection from U6 to the first CD4053 switch feeding its serial input.

What's still missing is switching logic, which I haven't worked out yet. For example, going forward and reverse will be straightforward, but there should be some logic on routing the random signal when switching between forward and reverse.

When I'd put that in, I'd planned on "reducing" the logic - IE, seeing if I could get away with fewer devices using MML rather than the dedicated gates I have depicted.

And, I haven't quite picked the tap points yet either. I sort of stopped working with this when it was beginning to look like a "fart in church" moment there Laughing .

Guess I should pursue it and finish it up. Of course, you're welcome to work with it/embellish it in the meantime.

Cheerio,
Scott


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ringer



Joined: Feb 20, 2007
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Location: montreal

PostPosted: Sat May 17, 2008 11:24 am    Post subject: Reply with quote  Mark this post and the followings unread

Hi Scott,

Thanks for clearing up the issues. I am reading and learning the Cmos Cookbook, hence the questions about the control lines.
I am so anxious about this. I have mapped the layout for this circuit, i just need to tie all the control lines together and will bread board it to confirm it works before I finish the layout.

Ok Scott, here comes creeperitous, since this going to be a new board and jumping the 4034's over to the new boards, you could add memory to it. Say an 8 position switch to select a pattern and vc addressing of the memory. I have had discussions with a friend to see it if it is possible with this new switching scheme, but I need to have the control lines in place before attempting the memory part. The basic logic and layout for the memory is done.

I have decided to go with sliders for my Klee, so the front panel is basically designed and I am almost done designing a pcb to mount all the switches, jacks , led's and sliders. I got these sliders with led's in the shaft and I have put an extra set 16 led's on the pcb and switch for the memory, should it be doable. I fear having all these flying leads around.

Keep the flame going Scott, this is very much worth it. It will become A Bionic Klee. :lol

Cheers,
R
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ringer



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PostPosted: Fri Aug 15, 2008 3:09 pm    Post subject: Reply with quote  Mark this post and the followings unread

Hi Scott,

Great uses for the Klee from the 101 thread. I got mine ready to go, but wanted to know if you got any further with the control lines for the above schematic done, many thanks.

Btw, your slide pot design is looking mighty fine, great work.

Can't wait to here to hear an example.

Regards,
Ringer
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Scott Stites
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PostPosted: Thu Aug 21, 2008 2:09 pm    Post subject: Reply with quote  Mark this post and the followings unread

Yikes Shocked - I coulda sworn I posted a response the other day.

Sorry, I just haven't gotten any further with this project - too many bright and shiny objects around here keep distracting my attention.

Take care,
Scott

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PostPosted: Sun Aug 24, 2008 1:54 pm    Post subject: Reply with quote  Mark this post and the followings unread

Hi Scott,


Sorry for asking, I am at the final stages of laying out my motherboard for sliders to avoid all the flying leads.I know you are busy doing projects with Thomas Henry and the appendage project, so I didn't want to interfere too much. I am still going slowly with the CMOS Cookbook and I need a little help with this one. Every time I read and layout from schematic, I learn something new.

Regards,
Ringer
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