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 Forum index » DIY Hardware and Software » Microcontrollers and Programmable Logic
Xilinx's MIG (Memory Interface Generator)
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JovianPyx



Joined: Nov 20, 2007
Posts: 1234
Location: West Red Spot, Jupiter
Audio files: 158

PostPosted: Fri Jan 13, 2012 9:47 am    Post subject: Reply with quote  Mark this post and the followings unread

While working on MIG again, I note some things that went over my head before.

And also - the feedback path on the Spartan-3E Starter Kit board is indeed present. This was proven by a friend who designed a test that causes the rightmost LED to flash if the trace is there and connected. It shows up in the schematic and the LED on all 4 of my boards flashes indicating that it is present.

The MIG will generate an interface either with or without a DCM. When allowed to add the DCM, all it will do is generate 2 clock phases, clk0 and clk90 for the interface. Even though you tell the MIG what the clock should be - it does not modify the frequency of the incoming clock. That must be done external to the DDR SDRAM interface.

I have two different routes I will persue - one is to continue working with MIG to see if I can make that work (not yet...) and the other is to see if it's possible to pump the Rick Huang interface (which I have working flawlessly) up to 133 MHz. Since I already use dual rank synchronizers to talk to the interface from the 50 MHz clock domain, synchronization between the 133 MHz and 50 MHz clocks is not necessary, so it should be fairly simple (at first look... I know how that goes).

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FPGA, dsPIC and Fatman Synth Stuff

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JovianPyx



Joined: Nov 20, 2007
Posts: 1234
Location: West Red Spot, Jupiter
Audio files: 158

PostPosted: Mon Feb 27, 2012 6:52 pm    Post subject: Reply with quote  Mark this post and the followings unread

I add this reply because I see this thread has ended inaccurately - and in a good way Smile

I returned my attention to a design posted elsewhere by Rick Huang which I had squirrelled away on my server. His project is an audio record/playback project using the SDRAM to store the audio samples. The code turned out to be nicely written (IMO) and I was able to strip away Rick's application from the interface to SDRAM for the Spartan-3E Starter Kit. With that interface, I was able to make echo/delay for several synthesizers. The interface runs the SDRAM at 100 MHz which while not the maximum speed (133 MHz) is more than fast enough for echo/delay and reverb.

_________________
FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.
Fruit flies when you're having fun.
BTW, Do these genes make my ass look fat?
corruptio optimi pessima
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martin200



Joined: Apr 13, 2012
Posts: 1
Location: MM

PostPosted: Fri Apr 13, 2012 5:33 pm    Post subject: Reply with quote  Mark this post and the followings unread

JovianPyx wrote:
Here is Rick Huang's widebus-recorder project. It's an audio record and playback design that uses the SDRAM on the Spartan-3E Starter Kit.

http://member.newsguy.com/~rhuang/FPGA/WideBus-Recorder.zip



Hello,

I'm new in FPGA. I'm looking for "WideBus-Recorder" project, but this link now don't work. Does anyone know where I can find it?

Best regards,
Martin
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