CD4017 timing question

[diablojoy]

Hi running into a brick wall on this one
A] anyone know the timing of the outputs of a 4017 and can confirm or repudiate the following
going off the timing chart on the data sheet visually it appears as if they overlap each other slightly ie output one only goes low after output 2 goes high and so on however the data sheet only states that the outputs are held high for one full clock cycle , now during physical testing of a particular cct i see some 50 micro seconds overlap which is massively longer than the less than 100 nano seconds or so i would have expected
hence my doubts as to the validity of the result and this question.

some back ground
I came across this working on a sequential switch using cd4017 / DG412 bsically the same as fonik's switch just 8 steps not 4 it is switching clock signals to 8 of hexinvertors sympleseq's . now obviously if the 4017 is holding each of its outputs for 50 microseconds after the full cycle clock pulse you get an extra 50 micro second pulse from the start of the next clock pulse into each sympleseq causing a double step of each sequencer
this is very much unwanted behaviour, So now i need a way of removing that pulse or at least circumventing it . Any and all idea's on how to do that are most welcome.

[Banjo]

I am having an issue that may or may not be related to what I think you are describing. I built a sequencer similar to a Baby 10, but using eight steps. My timer is a 4049, and a 4017 to sequence. I don't have the schematics in front of me nor any data sheets, so I can not look up the timing. It seems as if I am getting an extra pulse or signal on my steps. Two tones for the price of one so to speak. I will look into what you are describing later on and see if that is causing my two for one tones.

[EdisonRex]

Maybe you guys can post schematics. It's difficult to say without looking at what you're trying to do. Normal propagation delay should be more like 50ns not 50ms, but that said, one needs extra logic to make discrete gates out of a 4017, as has been noted here from time to time.

[diablojoy]

yeah i agree about propagation delays, max all up should be less than
200 nano seconds for the particular cct in question however i dont think it is a question of propagation delays here what is concerning me is an overlap in the stepping where each 4017 output remains high even after the next output of the 4017 has switched high and remains high for far longer than expected well [50 microseconds or so]

schematic of seq switch and very simple block diagram of use attached

note the sequential switch is based on fonik's very nice design

now on my scope what i am seeing is this
probe A is measuring the main clock signal in - a 50% duty cycle clock at roughly 300 hz
probe B is measuring the clock signal entering symplseq 1 [ they all test the same i checked]
the divider is at div by 1 so each clock tick should step each symplseq once and also step the sequential switch one step so each symplseq should only step once each in turn [ the divider has been calibrated and the cct has been tested with out the divider in place - no differance]
ON probe B I see the clock signal fine but also see another pulse in line with the start of the next clock pulse, of about 50 microseconds in duration and of equal voltage to the the main clock , each sequencer naturally double steps- not good
mulled this over in my head for a while and rechecked as much as possible and came to the conclusion that the most likely cause is an overlap of the 4017 outputs hence the original question
50 microseconds seems a very long time for a cct output to from high state to low
i have never seen any schematic here showing pulldown resistors used on 4017 outputs but perhaps i should try that ?

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[Dave Kendall]

Hi mate.

Hmmm - a puzzler...

Couple of ideas..... If you haven't already, try measuring the incoming CLK and the Q outputs directly on the 4017, and comparing them on the dual sillyscope. That will show if the problem is there, or in or around the DG412s.
One way to do that might be to hook up say, the 4017's Q1 and Q2 outputs to an AND gate and look at its output. That will show if there's an overlap at the 4017 Q outputs, or more specifically, if Q1 is slow to return to zero.....

I don't think pulldown resistors on the Q outputs for the 4017 would help. CMOS fanouts are large, and I can't see any floating inputs on the DG412s, so that *shouldn't* be a problem.
Another thing to try is to temporarily disconnect the RESET input sub-circuit with the transistors, and the extra manual RESET and CLK circuitry to the 4017 to see if they are having an effect on things. Basically simplify the circuit as much as possible, and see if the problem remains/changes.
(From memory, a 4017 with several connections via diodes to the RESET input can be quite picky, although that may just have been the way the M2C was wired up when I was testing it).
Finally, see what happens when temporarily bypassing the 4 x 40106 inverters on the clock line, and see if (where) the problem moves.

It can often help lots to temporarily remove sub circuitry, so as to rule it out of the equation (or not!)

Good luck - keep us posted.

cheers,
Dave

[Banjo]

Looking at your schematics, I can not say what is happening, due to my own lack of knowledge at the moment. I think what is happening in my situation, is that while my cv out is determined by whether or not it's corresponding switch is on or off. My gate however is running free. My oscillator, VCA, or envelope is getting the gate signal and is triggering which is producing my "second tone". Not being in front of my rig, I can not tell you how my patch cords are configured, but I am sure that is what is happenening. Perhaps there is some similarity in your situation. Like I said before, I really don't have the experience to say what is happening in your case

Paul, I'm not sure if what you are referring to discrete circuits would remedy my situation, but I think I have a solution for it. A simple solution would be to just add an on off switch to the gate out for each step. I like that idea, as it would add an extra dimension of creative possibilities to the system.
Diablojoy, I still don't know if my situation relates to yours of not, but I am curious about it regardless.

[Mongo1]

It looks to like the propagation delay through the CD4017 is causing the problem. The clock running through those 4 invertors is getting to the final stage before the enables are ready. So you get a little bit of the next clock pulse on the output.

Normally I'd suggest retiming some of your signals but the only thing you've got to work with is the clock you're trying to output. That makes it pretty tricky.

You might try (and you didn't hear this from me) inserting a small RC time delay between two of those inverter stages to see if you can add a little more delay into the clock line as it heads to the DGs. Yech!

Gary

[diablojoy]

Dave all good ideas
you are correct about the pulldowns - no effect
proved the issue last night to the 4017 just as the way you suggested
also tried miminalising the cct - so not the reset circuitry
dont know the reasons behind designing the 4017 with such a massive overlap on the outputs but there it is. I must go with the empirical evidence
something to remember.

Banjo I doubt we have the same issue with just a straight sequencer
what i am looking at would not be an issue with that sort of circuit
post a schematic of what you have and we can go over it.

Mongo the 4 invertors are being used to delay the switched clock some 240 nano seconds to allow for the propagation delays inherent in the 4017 approx 170-200 nanoseconds + a small amount
however since it seems the outputs of the 4017 hold for far longer than i expected they do not acheive their intended purpose . I originally tried removing them and i also tried increasing the delay right out to some 1600 nanoseconds its just not enough .
So i either need to insert a cct that does not effect the pulse length to delay the incoming switched clock pulse by more than 50 microseconds
[a small BBD cct perhaps came to mind] harder or i need to provide enough slew to the start of the pulse so that it is under the 50% level trigger point of the cmos for greater than 50 microseconds and then recondition the clock pulses again after the DG switches though this would of course have a small shortening effect on the pulse length

[Bogus Noise]

I know you've said that it seems a bit long for a propogation delay, but have you tested this kind of 4081 AND circuit already? Might be worth trying, if only just to fully rule the delay out! Got the schematic from someone else's post on here, and it solved the double triggering problem nicely. I'm using a 4011 for a clock circuit.

http://synthforum.nl/forums/attachment.php?attachmentid=50902&d=1251475305

[diablojoy]

thanks for the interest
i have gone down that road already with a 4081
does not solve this particular dilemma however
I dont think its so much a propagation delay issue rather something in the design of the 4017 itself , where each output is held high for some 50 microseconds in time after the next output has gone high , so for 50 microseconds in time 2 outputs can be active at once , normally no one would see this but as i am attempting to multiplex the same clock as i am
clocking the 4017 with it does throw a spanner into the works
i do have another couple of ideas to check and I believe i perhaps have a solution to get around it at least . now just need to breadboard and try it.

[EdisonRex]

[Banjo]

So even if I add an on off switch to my gate signal, the issue that diablojoy is having will still be present in my set up. If the clock signal from the 4011 in his case, and the 4049 in mine, get a pwm to shorten the clock signal, the delay caused by the transit from high to low, will then fall within the desired time frame. Just a thought. I hope I am explaining my idea correctly. The theory at least with my limited knowledge would work. If I have time today, I might have to breadboard a 4011 clock and experiment. I wish I had an oscilloscope to see what was happening.

[Banjo]

I just looked at the picture of your scope, and the spike is at the low to high transit point, and not the high to low. I am guessing that a pwm would work with that as well if my theory is correct.

[fonik]

wild idea, probably: you want to switch clock signals only, don't you?
maybe you can convert the 4017 gates to fixed length pulses? not very short pulses. long enough to open the analog switches for letting the clock thru, short enough to get rid of the doubled clock?

[diablojoy]

interesting concept matthias
not certain but would that not mean it could only be optimised for one switching rate and therefore clocking rate so the operating range of the sequencers would be decreased ok at slow rates but as rate was increased
problem would reemerge

I think i have come up with a solution last night but will need to breadboard it first though
my plan at the moment is to use a very cut down barebones and readjusted version of yusynths gated slew cct to provide some slew to the front end of the switched clock pulse going into the 40106 array which should then resquare up the pulse before going to the DG switches thus shortening the front end of the switched clock pulse only. The clock pulse going to the 4017 of the sequential switch is unaffected and remains as is.
I will make the slew adjustable by a trimmer and try out some differing capacitor values to get the time constant to the sweet spot I only want to shorten it enough to remove say approx 75-100 microseconds to be safe . this way i should still have the bonus of variable gate length from clock PWM and the full rate range at the actual sequencers
anyway its just theoretical at the moment but we shall see.

[fonik]

shortening the front end or the back end of the gate, dies tht matter?> otherwise you have the similar idea, if i got it right. and in both cases you would hve to find the >sweet spot< htat serves you the best. make the pulse as short as possible but long as necessary.

[fonik]

both solutions would affect your sequencers gate out length, though.

[diablojoy]

[diablojoy]

some success last night eventually yay
I hate breadboards even more now though
did eventually get rid of the double stepping though
will try to draw up a board tonight
very small only a TL072 and a few componants

[diablojoy]

for a moment there i had a thought of a proper way of removing the overlap of the 4017 outputs directly the way matthias suggested but not sure which chip may work the way i want
if the 4017 outputs are each put through a one shot cct to create a trigger
and then that trigger is used to trigger a chip xxxx while the original clock
signal is used to latch said chip xxxx then the resulting output should be only as long as the original clock signal is in a high state this can then be fed to the logic in of the relevent DG switch. would need to be one cct per 4017 output used so in my case 8 ccts
I am showing my complete ignorance here as i dont know of a chip that does that, suggestions anyone ?

[fonik]

maybe trigger flipflops? these could then control the analog switch?

[Banjo]

I don't know if this will help, but I was looking for related info on the web and this caught my eye.

http://www.analog.com/static/imported-files/rarely_asked_questions/4000_Series_Article.pdf

Some of the schematics in here might spark an idea for a solution.

[Tim Servo]

Not to throw a wrench in the works, but I'd say it looks like time to try some other chip besides the 4017. A combo like an up/down counter (40193) and a multiplexer / decoder (4028 = 1 of 10, 4512 = 1 of 8 with tri-state outputs, and others) would be my first suggestion. This may sound like a more complex solution than a single 4017, but by the time you end up with additional chips and delays to make the whole thing work properly, it may actually be an easier way to go.

http://en.wikipedia.org/wiki/List_of_4000_series_integrated_circuits

Just a thot.


Tim (Wrench Works, Inc.) Servo

[diablojoy]

AH sorry tim that last posting of mine is really more of a bit of an excercise to find a better solution to the 4017 overlap issue
Matthias's earlier suggestion got me thinking along different lines
I already do have a way round it that will work for my sympleseq64 build but it is more of a way of sidestepping the issue really. Acceptable to me for my build, but perhaps a better solution is possible . someone may read this one day and find some usefullness in it.

Matthias indeed a flip flop. I was thinking of it wrongly originally as with a flip flop some impetus is needed to change the Q state back to low
and i saw no place to get that from of course if the flip flop also has a reset input, that can be used to force Q low and if the reset pulse is derived from the falling edge of the original clock pulse that should fullfill the requirement .
so in summary the flip flop Q output goes high in response to a rising edge trigger taken from the output pulse of the 4017 output and then is forced low again by a falling edge trigger from the clock pulse signal into its reset pin . result should be a usable pulse almost exactly matching the original clock , excepting some propagation delay of course and yes it would be a very good signal to then control the analog switch with .
EDIT: half of a cd4013 D flip flop per 4017 output and some extra circuitry to get a falling edge pulse from the original clock signal to send to the reset pins, should work fine i think.

[diablojoy]

banjo thats a really good article thanks