External reset and run step one for 4017 based sequencers

[diablojoy]

something that came about whilst working through my
SympleSEQ64 build.
A question was raised as to the ability to externally reset 4017 based sequencers and actually play from step 1 not reset to step 1 only to then hear step 2 play as the next clock pulse ticks over the sequencer
so i came up eventually with a small simple circuit to do just that.
It has been tested with Foniks VCPS sequencer as well as SympleSEQ
using both Dave kendals M2C module and Foniks Master clock
as clock sources, works quite well in all cases.
note : +10 volt clock and reset trigger or gate signals are required
Really good to use with the M2C as you can always start from step 1
when recording .
the circuit is very simple only 2 chips and a few ancillary components
The board as shown is envisioned as an add on board for existing 4017 based sequencers simply wired between the reset jack and the reset in point on the sequencer board the clock input is just tapped from the clock in jack or internal clock .
I will be adding this circuit to all my Fonik VCPS sequencers and also probably to my fonik sequential switches [I have yet to test with those yet, I see no problems there though]
the circuit could also be incorporated into any new 4017 based designs
where there is usually a couple of spare 40106 sections available.
Anyway hopefully other people also find this usefull.

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single reset and run step one bottom foil.pdf
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[saint gillis]

Thanx Diablojoy for solving this boring problem!
Yusynth uses some discrete Schmitt triggers with 2 npn transistors, might be usefull...
http://yusynth.net/Modular/Commun/DIVIDER/ClockDivider-sch.gif

[diablojoy]

[saint gillis]

Hello DiabloJoy, maybe it is better to share my adventures here...
So.. "Clock">"Clock divider">"Sequential Switch Clock in"
And "Clock">I/O and I/O1>Sympleseq#1 clk in .. I/O2>Sympleseq#2 clk in.. I/O3>Sympleseq#3 clk in ..I/O4>Sympleseq#4 clk in

I ve made several "Reset & run step1 circuits" for the clock dividers, the sequential switchs, for every 4017 indeed
It works quite fine, I ve just got a last problem (hope it will be the last ) :
When the Sequential switch is on I/O2, I/O3 or I/O4 no problems after reset it runs on I/O1 ! great
But when the sequential switch is on I/O1 after reset it runs I/O2 instead of I/O1 again...

Another strange thing is that when I make a manual reset and then some manual steps it always starts on I/O2 rather than I/O1 (I/O1's led goes for a very tiny tiny little bit of light at the same moment as when I/O2 goes on!)

http://modular.fonik.de/pdf/SeqSwitchV2.pdf I ve put D3 and D4 cathodes to go on the "Reset & run step1 circuit" the output of the circuit goes with a diode on the reset pin of the 4017

[diablojoy]

[saint gillis]

In fact the manual reset was also routed through the "reset & run1" circuit; it was working as it should after a lot of "kludges" I ve disconnected the 1M resistor going from the reset input to the ground (on the "reset & run1" board) then I ve also removed the two 47k resistors on the sequential switch going from the 4017 "reset" & "clock" pins to the ground; then I had some correct behaviours with the push switchs "manual step" and "manual reset", it was actually correctly running step 1 after reset in any sort of case!

But always the same problem with the external clock... Maybe the problem is coming from the clock dividers: for instance I divide the clock each 8 steps, the divided clock goes in the sequential switch "clock input" to switch to the next sequencer each 8 beats, in that case when I m on I/O2, 3 or 4, after reset it runs I/O1, but if I m on I/O1 after reset it runs I/O2!!!
Another strange example: now I m dividing the clock each 16 beats (1st clock divider dividing each 8, this goes in the 2nd clock divider dividing each 2 beats), same thing the divided clock drives the sequential switch : Now I play less than 8 beats on I/01, stop, reset, it runs I/O1, I play again less than 8 beats, stop, reset, it should run I/O1 again but it runs I/O2, I play again less than 8 beats, stop, reset, it runs again I/O2, I play less than 8 beats, stop, reset, it runs I/O1... if I stop & reset on I/O3 or 4 no problems it runs I/O1...
Now if I play more than 8 beats on I/O1, stop, reset, it runs I/O2, I play again more than 8 beats, stop, reset, it runs I/O1, etc..
Exactly the same behaviour as what I ve just described if I divide more the clock (I use one Yusynth clock divider going through the other so for instance 8X3+24 or 8x4=32 etc etc untill 8x8=divide each 64 steps)

The two clock dividers got each one a dedicated "reset & run1" circuit too..

Must be something logical but it hard to understand...

[diablojoy]

[saint gillis]

Here is the patching diagram

For the clock divider, I ve made a smallest version with only 2 dividers (instead of 3) http://yusynth.net/Modular/EN/DIVIDER/index.html

[diablojoy]

hmm had a look over the yusynth divider last night
cant see any theoretical reason for it to not work
nor can i see any reason for it not to work as it should from your
diagram. I think propagation delays can be discounted as the problem.

you probably would not need 2 reset and run step one circuits for the dividers one should be able to drive both so that part could be simplified
a little. unless of course that is required for resetting the dividers individually when wanted, still might be worth checking out.
does it fail to reset correctly everytime or is it a percentage chance ?
also have you tried swapping out reset and run step one boards with ones known to work elsewhere say from one of the symplseq's ?
only other thought i have for the moment is to check the level and shape of the clock pulse and reset pulse going in to each section with a scope
you would probably need access to a storage scope though to be able to compare properly

[saint gillis]

[diablojoy]

[saint gillis]

yes I ve tried to intervert the chips, same result, I also tried to intervert the 4017 in the diviers, in the sequential switch etc...
I ll be on the road for a while I come back next week to continue working on this...

[saint gillis]

Hello Diablojoy!
I m back, I ll try to describe precisely what's going on
Still the same : when my sequential switch is on I/O2, I/O3 or I/O4, after reset no problems it runs I/O1, great!
When the sequential switch is stopped on I/O1, reset, it starts again on I/O1, good, then I stop it again on I/O1, reset, the 2nd time it runs I/O2 instead of I/O1 ... If I m playing some 8 bars sequences (for example) this problem can be really boring, you know I m listening to the sequence, stop, reset, ok, 2nd time, stop, reset, it starts on the 2nd sequencer, not good...
I ve tried the experiment on a Sympleseq, same thing, you stops on step1, reset, start>runs step1, stop quickly on step 1 again, reset, >it runs step2 !
Had never noticed that on a Sequencer because it never happens... on a sequential switch where the steps can be quite long it becomes a bit boring..
I hope I m not telling bullshit, waiting for your opinion!

[diablojoy]

sorry saint gillis i had another thing i was looking into
yeah i think i am going to have to do some more testing
i have very occassionally seen it start at 2 myself . It seems to be only if i send 2 resets signals very close together on mine
not sure why yet . maybe reset pulse length needs optimising better
thought i had it pinned down but will try some new values.
but its gonna have to wait for the weekend now
will get back to you.

[saint gillis]

[saint gillis]

Hmmm, maybe it can help you :
When I m clocking the sequential switch (& also its dedicated "reset & run1" circuit) with the "manual step", it works perfectly!
When clocking it with an external clock, the bug I ve described occurs, same thing for the sympleseqs...



http://modular.fonik.de/pdf/SeqSwitchV2.pdf

[diablojoy]

[diablojoy]

It has taken a while to pin down the circumstances under which this fails
but i think i am getting somewhere and now know why i didnt notice it so much before. previously i have been stopping and starting the clocking from my DAW using a start pulse to provide the reset signal therefore it was fairly random in nature I thought that would be the best way to test, i was wrong had i been using a divider to send in a reset i probably would have had it set at some point to divide by 8 and would have seen this straight away
I seem to be getting incorrect stepping after external reset only on multiples of the 8th clock tick and also if 2 external reset pulses are received within 8 clock ticks of each other [slightly different case and an expected result]
Now with no dividng going on , every 8 clock ticks equates to the last step on my 8 step sequential switch where it has its own reset point as output 9 is hard wired to reset in so 2 resets basically occuring on top of each other

With a 4 step sequential switch i think the issue should occur if the reset signal were at multiples of 4 clock ticks but if i am right it should be fine on other divisions so fail at 4 - 8 - 12 - 16 and so on but ok at say 5 - 6 - 7 - 9 - 10 - 11 - 13 - 15 -17 - 18 - 19....Saint gillis can you possibly check that out please otherwise it will have to wait till i can build another divider to test with.
I am really not sure if this issue can be gotten around at the moment a real brain teaser to be sure.

[saint gillis]

Hmmm, before taking this way I 'd like to describe you something :
Let's forget the clock divider, let's just take a sympleseq and a "reset & run1" circuit : you let the sympleseq making some cycles and you stop it on step 1, let's reset, then start, it runs step1, you stop it again when it is still on step 1, let's reset, then start, it runs step 2 (instead of step 1 as we would expect)
Have you noticed that?

[saint gillis]

And when I'm making a manual step, the problem disappears, so as you said it could be a solution to stretch the clock impulsion going into the "reset & run1" circuit, unfortunately I don't have a 5p capacitor to try what you advised before (10pico is the smallest value I got for now)

[saint gillis]

I hope we don't have some kind of communication breakdown, english is not my main language but I think I understand what you say, hope what I m saying is clear enough

Now I ll take the risk to give you some more information, it is not so related with our main focus, but I just wanted to tell you that I had to remove R12 on the sequential switch (http://modular.fonik.de/pdf/SeqSwitchV2.pdf) to have the "Reset & run1" working properly, otherwise it kind of starting on step2...

Hope this is not confusing...

[diablojoy]

[saint gillis]

[saint gillis]

I confirm that I ve just tried to stretch a bit the clock pulse through an ADSR (adding a bit of release) and it works perfectly (no bug on step 1)...
So we need a simple way to stretch the clock on the "reset & run1" circuit, do you think it could be possible with a few discret components or the free Schmitt triggers on the 40106...

[saint gillis]

Some people advised me to use a NE555 as a monostable, this circuit will become bigger than the sequential switch
By the way I ll be again on the road for a while...

Let's keep informed