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blue hell
Site Admin
Joined: Apr 03, 2004 Posts: 24079 Location: The Netherlands, Enschede
Audio files: 278
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Posted: Sun Apr 17, 2011 8:31 am Post subject:
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JovianPyx wrote: | Ok, here is the Mozart piece. |
Nice one Scott! _________________ Jan
also .. could someone please turn down the thermostat a bit.
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emeb
Joined: Dec 16, 2008 Posts: 35 Location: Arizona
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Posted: Sun Apr 17, 2011 9:37 am Post subject:
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Hi,
I've been lurking on this thread for a while and thought I'd throw out a few comments:
* First, kudos to Scott. He does amazing things with FPGAs and I'm looking forward to what he can do with a dsPIC.
* For what it's worth I've got a bunch of dsPIC and FPGA related projects documented on my website here:
http://members.cox.net/ebrombaugh1/synth/index.html
Schematics, PC boards and source code included for most of them.
* It's worth noting that several of the dsPIC designs at the site linked above are the basis for the Synthesis Technology E3x0 and E5x0 series of Eurorack modules. I did a lot of the software prototyping on these little boards before we went ahead with the form/fit/function development. Based on my experience with those modules, the direction you're going using dsPICs in this thread seems feasible.
* Sample rates for the '802 DAC - The clock rate for the on-chip DAC is closely tied to the rate that the processor runs, although there is some flexibility due to the various dividers in the clock generator. In some of my oscillator applications, I usually run the dsPIC CPU at about 39MHz and then run the DAC at about 98kHz - this seems to give a good balance of sample rate vs processing throughput. For audio effects the sample rates don't need to be as high because you're not as worried about aliasing, so those will typically run the CPU at 23 or 39MHz and then clock the DAC in the 30 - 40kHz range.
* Programming language: MCHP has a decent (not *great*) C compiler for the dsPIC available for free. It integrates nicely with MPLAB and I've had pretty good luck using it for some of my more recent projects. You don't want to try using it to do high-performance DSP coding, so I use assembly for that, but I've found it works nicely to code interrupt service routines which handle signal processing in assembly, and then the low priority 'big loop' code for housekeeping works fine in C. I also have had good luck building up a personal library of C callable assembly functions for common calculations, like exponential conversion, filtering, nonlinear functions, etc. Also, parsing MIDI in C is worlds easier than trying to do it in assembly...
* Someone mentioned that the DACs can be noisy. True. Also from time to time you may come across a dsPIC with bad DACs. I've got no idea how those slip through the manufacturing testing process, but usually just swapping them out works.
Keep up the good work. I'll be lurking so if there's any way I can contribute just gimme a shout... |
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loss1234
Joined: Jul 24, 2007 Posts: 1536 Location: nyc
Audio files: 41
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Posted: Mon May 09, 2011 12:59 pm Post subject:
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I will be watching this post with excitement! I would love to find a SIMPLE SDIY DSPIC project!
I have been finding tons of synth related AVR projects...But everyone keeps telling me the DSPIC has the power to do amazing things...sadly, unlike the AVR, it seems much harder to find projects to learn from, and the code seems more complicated...(hence the need for projects to learn from
anyway, thanks for doing this! _________________ -------------------------------------------- check out various dan music at: http://www.myspace.com/lossnyc
http://www.myspace.com/snazelle
http://www.soundclick.com/lossnyc.htm http://www.indie911.com/dan-snazelle |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Mon Nov 07, 2011 5:34 pm Post subject:
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I've added DDR SDRAM to the FPGA design for this. 41+ seconds of delay.
I also bought some Microchip 23K256 ICs, these are 32K byte SPI SRAM ICs. Using the CS pin to select the RAM being accessed, I should be able to put 2 of them on the SPI port of the dsPIC and have 32K words for a 740 mSec delay at 44.1 kHz sample rate. This lives all of the internal dsPIC SRAM free for DSP magic. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Dan Lavin
Joined: Nov 09, 2006 Posts: 649 Location: Spring Lake, Mi, USA
Audio files: 21
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Posted: Fri Sep 21, 2012 1:13 pm Post subject:
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Scott: this is still the flute you're porting over to the dspic, correct? _________________ Synth DIY since 1977! |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Fri Sep 21, 2012 2:33 pm Post subject:
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Actually, no, I'm being more adventurous. This will be a 3 dsPIC project that will hopefully be a 12 voice Karplus-Strong harp synth.
I have the MIDI hardware working along with a TTY port, I can so far send the hex value data from MIDI messages to a UART/TTY output which I connect a COM port on my PC.
This will soon turn into a MIDI controller (I have PicoBlaze uC code I can convert).
Trying to get the MIDI UART to interrupt... _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Tue Sep 25, 2012 7:53 pm Post subject:
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I've now got a board that can receive MIDI data on one port and send the same data at 115.2 kilobaud to a PC COM port. The MIDI receive stream is interrupt driven. The application reads MIDI bytes and translates them to hex ASCII characters sent to the output UART.
Thank you to Blue Hell. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Dan Lavin
Joined: Nov 09, 2006 Posts: 649 Location: Spring Lake, Mi, USA
Audio files: 21
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Posted: Fri Oct 05, 2012 7:27 pm Post subject:
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So even with 3 dsPICs it looks like a low parts count, or maybe I'm just wishful thinking here!? _________________ Synth DIY since 1977! |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Fri Oct 05, 2012 8:03 pm Post subject:
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My hope is to get 8 voices minimum out of the synth. In this case, one dsPIC will be a MIDI controller and voice assigner, the other 2 will be voice engines. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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Cynosure
Site Admin
Joined: Dec 11, 2010 Posts: 966 Location: Toronto, Ontario - Canada
Audio files: 82
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Posted: Fri Oct 05, 2012 8:58 pm Post subject:
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It looks like it is coming along well. I can't wait to hear it! _________________ JacobWatters.com |
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bubzy
Joined: Oct 27, 2010 Posts: 594 Location: United Kingdom
Audio files: 64
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Posted: Sat Oct 06, 2012 3:51 am Post subject:
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looks like an arduino would be neater
*hides* _________________ _Richard_ |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Sat Oct 06, 2012 5:35 am Post subject:
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Probably would be neater, but then it would be dsPICable. And just think of all those MIPS... _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Thu Oct 11, 2012 3:28 pm Post subject:
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I now have 2 dsPICs running at 40 MIPS with a 10 megabit per second one-way SPI link between them. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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Dan Lavin
Joined: Nov 09, 2006 Posts: 649 Location: Spring Lake, Mi, USA
Audio files: 21
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Posted: Thu Oct 11, 2012 6:24 pm Post subject:
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Good job, Scott. I'm guessing this is the hard part and it's all downhill from here....or am I being overly optimistic? _________________ Synth DIY since 1977! |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Thu Oct 11, 2012 6:59 pm Post subject:
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Dan Lavin wrote: | Good job, Scott. I'm guessing this is the hard part and it's all downhill from here....or am I being overly optimistic? |
The dsPIC SPI module was designed to be versatile enough to connect to any sort external SPI device that can run at 10 megabits per second or less. This means the module accepts many parameter choices - all of which have to be correct or it won't work. I was also a bit worried about the electrical end of things. 10 megabits per second is essentially RF and as such, RF practices need to be observed. Clock and data lines should be the same length - but not too long. Under some conditions, buss termination resistors might be required (for long wires). Fortunately, it works with an 11 inch cable and no termination resistors. The signals (clock and data) look very clean and crisp on an oscope.
So for me, this was a big deal and yeah, it should be easier here on out.
Next is to get the DAC making a signal.
After that to get the ADC to acquire CVs from dsPIC pins.
And finally, I get to write the synthesizer. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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Dan Lavin
Joined: Nov 09, 2006 Posts: 649 Location: Spring Lake, Mi, USA
Audio files: 21
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Posted: Thu Oct 11, 2012 7:29 pm Post subject:
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Quote: | After that to get the ADC to acquire CVs from dsPIC pins. | Is this for knob tweaking of timbre parameters or 1V/octave pitch control like an analog synth? I guess I figured it would be midi controlled, but hey whatever! _________________ Synth DIY since 1977! |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Thu Oct 11, 2012 7:50 pm Post subject:
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This first project will be a MIDI controlled polyphonic harp synth based on Karplus-Strong string models. Two parameters that affect the synth's timbre are the loop's lowpass filter cutoff frequency and a linear damping value. These two parameters will be set by pots (supplying the CVs to the dsPICs). It could easily be modified to accept CVs generated by other devices. I am also considering a module that will accept an additional CV for pitch. In the modular version, the pitch CV would be captured and stored when the trigger occurs. Because it will have a sustain pedal input, it would be possible for a modular owner to use a sequencer to play the harp - even in polyphony because of the sustain pedal. Chords could be played with a sequence of pitch-change and triggers that are closely spaced in time. I will have to talk with modular friends to determine if this is feasible with the kind of equipment that they already own, so at this point the module version is only an idea. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Fri Oct 12, 2012 1:05 pm Post subject:
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Data reliability test passed.
The test was designed as follows:
A transmit dsPIC was programmed to generate a 16 bit pseudorandom number using a 32 bit LFSR. The low word is used as data. The 32 bit SPI message was create using the low word and it's ones complement. This is then sent to the receiver with 1 uSec of dead time between transmissions.
A reciever dsPIC was programmed to receive the 32 bit messages (using interrupts). The received 32 bits of data is loaded into 2 registers. One of the registers is ones complemented and the two are then compared. If equal, the transfer was good. Errors cause a period to be sent to a terminal session using a UART set at 115.2 kbaud. As long as the terminal session has a blank screen, everything is fine. I tested the system by running it for awhile noting the blank screen. If the SPI connection is disconnected and reconnected, I get dots.
Both dsPICs were run at 40 MIPS with SPI set for 10 megabits per second. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Mon Oct 15, 2012 9:56 am Post subject:
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During my testing of SPI reliability, I found that a flourescent work light near the boards would cause SPI errors when switched off. I will add termination resistors to hopefully abate that behavior. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Mon Oct 15, 2012 2:49 pm Post subject:
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After reading about termination, I decided on 1K resistors to ground and +3.3 on both SCK and SDI. The resistors are on the receiver end of the cable.
When testing after I added these resistors, the errors generated by turning off my flourescent work lamp stopped. I do not know if this termination will work in other environments. From what I've read, 1K is a rather light termination. I want the current as low as possible. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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blue hell
Site Admin
Joined: Apr 03, 2004 Posts: 24079 Location: The Netherlands, Enschede
Audio files: 278
G2 patch files: 320
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Posted: Tue Oct 16, 2012 7:11 am Post subject:
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Ideally termination is on both sides and has the same impedance as your cable ... a twisted pair cable impedance calculator :: http://www.eeweb.com/toolbox/twisted-pair . It'll all be a bit of an approximation of course, when your cable is shorter than about lamba / 6 it should not matter too much anyway ... hmm10 MHz is 30 meter or so ... so for cables over about 5 meter it might become an issue.
Two times 1k means 500 Ohm termination, which is not really that high I think. _________________ Jan
also .. could someone please turn down the thermostat a bit.
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Tue Oct 16, 2012 7:50 am Post subject:
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As I said, my termination is light and doesn't represent a "fix all" for all environments. Readers should not take it as the absolute best solution, only that it worked for me in my lab.
Since the SPI signals look very clean on my oscope (no reflection that I can see), my intention was mainly to surpress external noise effects, which apparently it did. My reading regarding termination would have put the resistors at around 270 to 330 ohms, but I didn't want that much current if I can help it.
In reading about SPI in particular, most opinions were that no termination is necessary at all given a short enough transmission line. 11 inches is considered quite short at 10 MHz and it ran fine with no termination - as long as I didn't turn that flourescent lamp off. Also, the SPI articles I read did not mention using termination at both ends (as is the case for a bus like DEC's Unibus - but this is an open collector bus). I did think that was odd, but went with a terminator at the receiving end only (as was described in several articles). I looked at the schematic for the Spartan-3E Starter Board (FPGA) SPI circuit which is spec'd to run at 50 MHz and has 100 ohm termination resistors to both rails at one end only. Works quite well.
There are many factors to consider with transmission lines, length being one of them. I do understand the theory, and surely a best effort terminator may well be at both ends and a much lower resistance, especially for a more significant length of wire - however, what I did works.
As always, your particular milage may vary. If you play with this stuff, you may indeed need heavier termination than I used. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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