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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Sat Nov 19, 2011 9:38 am Post subject:
32 K byte SPI SRAM |
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I have two Avnet Spartan-3A 400 development boards. These boards have no external RAM, so any designs I did with them had access only to the RAM inside the FPGA.
I bought some Microchip 23K256 I/P SPI SRAM ICs to use with the FPGA board. The SRAM ICs are spec'd for a max SPI clock rate of 20 MHz. I was able to wire up a piece of stripboard to an IDE cable to plug into the board's 40 pin GPIO connector. The stripboard has 2 of the ICs connected using separate SPI busses. This allows data transfers of 16 bits instead of only 8.
After much banging and swearing, I got it working. I had a board construction error and many driver state machine problems, but it's now working. I've written a simple RAM diagnostic design that writes the inverted address as data, then reads back and compares, increment address and repeat.
The test ran overnight with no errors at SPI clock rate of 25.0 MHz. So the test is actually overclocking the SRAMs. And the ICs run cold.
Here's a link to the SRAM page on Futurlec: http://www.futurlec.com/ICRAM.shtml They sell for $1.35.
Nice cheap way to get about 0.743 seconds of mono delay at 44.1 kHz sample rate.
EDIT ADD: The RAMs, while they passed the simple diagnostic test, did not function correctly in a delay effect when run at 25 MHz SPI clock. They did, however, function correctly when clocked at 20 MHz in the same application.
EDIT ADD: These RAMs, produced by Microchip seem like a nice addition to a dsPIC. The dsPIC has a built in SPI port which does all of the ugly SPI stuff without dsPIC code. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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cloudscapes
Joined: Feb 09, 2004 Posts: 100 Location: Montreal
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Posted: Sun Nov 27, 2011 2:21 pm Post subject:
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yep, nice little chips. I used them for a granular looper/sampler. though only at 10-ish khz. the bottleneck was the 8-bit AVR, not the ram chip. _________________ Sonic Crayon DIY effects lab |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Sun Nov 27, 2011 3:26 pm Post subject:
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So far, I've written several diagnostic tests. All of them work up to 20 MHz SPI clock. Some work up to 25 MHz SPI clock. Patterns are all zeroes, all ones, 0x5555, 0xAAAA, data=address, data=inverted address. These are written to each location and checked as soon as written. There is also random data test where all 32K is written with a seeded LFSR. It is reseeded to produce the same sequence for the read pass. All of these work.
What is still vexing me is that I've been able to integrate the RAM as a part of a synth project, it works only marginally. I hear the instrument and the delayed playback has noise in it. Of note might be that the design is croweded at 74% of the slices available. This causes a timing violation with respect to the IO pads used for the SPI busses. The violation states that it takes too long for a signal to go from it's last flip flop to the IO pad. I need to find a way to force that flip flop to be in the IOB (IO buffer). _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Mon Nov 28, 2011 7:50 am Post subject:
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I was able to tell ISE to "try" to place final flip-flops to FPGA pins inside the IOBs. This reduced the amount of the timing constraint violation and at the same time greatly reduced the echo noise I hear.
This is telling me that the crowded nature of the design (74% of slices) has made it difficult to efficiently route the signals going to FPGA pins.
I'm not sure how successful I will be at this, but the next step seems to be to lean the design. There are now some 14 block RAMs available, so perhaps I can eliminate some of the distributed RAM allocation in favor of block RAM and reduce the numbers of LUTs used as small RAMs.
Since the violation concerns the CS pin on the SRAM, I might be able to simply move that one clock earlier and eliminate the noise entirely??? Hope springs eternal. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Mon Nov 28, 2011 4:38 pm Post subject:
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I finally have it working correctly in the bell synth.
As I looked at the timing constraint violations, I saw that they pointed to two of the pins I was using for the SPI interfaces.
I knew that if I converted the SRAM board from 2 parallel SPI busses to a single shared SPI buss, I could eliminate 3 FPGA pins.
Sure enough, while this is slower (twice as long to read or write 16 bits), it solved the timing problem. It now takes 256 system clocks to do the read and write work, but that's less than the 768 allowed, so it works. All of the noise on echo is gone! _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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KammutierSpule
Joined: Feb 07, 2008 Posts: 40 Location: Aveiro - Portugal
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Posted: Thu Aug 30, 2012 9:49 am Post subject:
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Hi
I was also looking for some type of volatile ram that use few pins.
I was looking for this SPI ram from microchip, but the size/price ratio is bad.. for almost the same price is possible to get an huge DRAM (that uses lots of PINs)..
Did you find any other options? with more bytes and lower price? |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Thu Aug 30, 2012 10:07 am Post subject:
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I'm not aware of anything with a better price ratio. Static RAM is the easiest to use, but it's not very dense because it uses about 6 transistors per bit. DRAM not only has many many pins, it also requires a controller that handles the refreshing and arbitration of data access with refreshing. There is also the more standard form of static RAM which is simple, but still pretty small and will have lots of pins. I chose the 23K256 because it was the biggest SPI SRAM I could find. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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KammutierSpule
Joined: Feb 07, 2008 Posts: 40 Location: Aveiro - Portugal
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blue hell
Site Admin
Joined: Apr 03, 2004 Posts: 24075 Location: The Netherlands, Enschede
Audio files: 277
G2 patch files: 320
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Posted: Thu Aug 30, 2012 2:04 pm Post subject:
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Interesting tho them large serial RAMs! _________________ Jan
also .. could someone please turn down the thermostat a bit.
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cloudscapes
Joined: Feb 09, 2004 Posts: 100 Location: Montreal
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Posted: Sat Sep 29, 2012 7:05 pm Post subject:
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thanks for the heads up! went and ordered a bunch. bout time they offer us an upgrade.
now give us 4Mb and 8Mb! _________________ Sonic Crayon DIY effects lab |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Sat Dec 01, 2012 12:46 pm Post subject:
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I have recently been successful in connecting a 23K256 SPI SRAM to a dsPIC33F using SPI at 10 megabits per second. The conductors for SPI are 2.5 inches long and have no termination (no termination is suggested by the manufacturer, Microchip). The device has run a random data reliability test for more than 24 hours with zero errors, so this looks to be a possible solution for external SRAM. At 10 megabits per second, a maximum data rate of 312.5 kbytes per second is possible. I am currently working to put this under DMA control since the code required to manage the SPI transfers is quite a burden (IMO). But the bottom line for now is that it works. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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cappy2112
Joined: Dec 24, 2004 Posts: 2465 Location: San Jose, California
Audio files: 2
G2 patch files: 1
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Posted: Fri Dec 07, 2012 6:25 am Post subject:
Re: 32 K byte SPI SRAM |
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JovianPyx wrote: | I have two Avnet Spartan-3A 400 development boards. These boards have no external RAM, so any designs I did with them had access only to the RAM inside the FPGA.
I bought some Microchip 23K256 I/P SPI SRAM ICs to use with the FPGA board. The SRAM ICs are spec'd for a max SPI clock rate of 20 MHz. I was able to wire up a piece of stripboard to an IDE cable to plug into the board's 40 pin GPIO connector. The stripboard has 2 of the ICs connected using separate SPI busses. This allows data transfers of 16 bits instead of only 8.
After much banging and swearing, I got it working. I had a board construction error and many driver state machine problems, but it's now working. I've written a simple RAM diagnostic design that writes the inverted address as data, then reads back and compares, increment address and repeat.
The test ran overnight with no errors at SPI clock rate of 25.0 MHz. So the test is actually overclocking the SRAMs. And the ICs run cold.
Here's a link to the SRAM page on Futurlec: http://www.futurlec.com/ICRAM.shtml They sell for $1.35.
Nice cheap way to get about 0.743 seconds of mono delay at 44.1 kHz sample rate.
EDIT ADD: The RAMs, while they passed the simple diagnostic test, did not function correctly in a delay effect when run at 25 MHz SPI clock. They did, however, function correctly when clocked at 20 MHz in the same application.
EDIT ADD: These RAMs, produced by Microchip seem like a nice addition to a dsPIC. The dsPIC has a built in SPI port which does all of the ugly SPI stuff without dsPIC code. |
We used these for a class I took recently.
I think they may be expensive compared to other ram varieties, but the instructor gave them to us for the class project.
Description: |
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FM25V10ds_r1-0-1.pdf |
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_________________ Free Tibet. Release the Panchen Lama from prison. Let the Dalai Lama return to his home. Last edited by cappy2112 on Fri Dec 07, 2012 5:36 pm; edited 1 time in total |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Fri Dec 07, 2012 4:53 pm Post subject:
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I looked up the FM25V01 part at Mouser which lists it at $6.03 each for quantities of 10. It is also a 16 kilobyte FRAM (where FRAM is nonvolatile ferroelectric RAM). As such, it's main advantage is that it's nonvolatile with 10 year retention span. This FRAM will run twice as fast as the 23K256, but dealing with a dsPIC SPI channel, this is no advantage because the dsPIC can do at best only 10 megabits per second.
The 23K256 is a 32 kilobyte SRAM (twice the size of FM25V01) and can be purchased for about $1.35.
23K256 is not expensive when compared with the FM25V01.
So the RAM one would select here would depend on the application. If nonvolatility is not required, then paying $6.00 for half the RAM would be quite expensive.
Also, Microchip has 23A1024 which is 1024 kbits (128 kbytes) priced at $1.73 and runs at the same speed as 23K256. Microchip shows that samples are available (which I am going to acquire). _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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blue hell
Site Admin
Joined: Apr 03, 2004 Posts: 24075 Location: The Netherlands, Enschede
Audio files: 277
G2 patch files: 320
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Posted: Fri Dec 07, 2012 5:01 pm Post subject:
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Oh, that Ferro Ram came down quite a bit in price then! _________________ Jan
also .. could someone please turn down the thermostat a bit.
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cappy2112
Joined: Dec 24, 2004 Posts: 2465 Location: San Jose, California
Audio files: 2
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Posted: Fri Dec 07, 2012 5:35 pm Post subject:
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JovianPyx wrote: | It is also a 16 kilobyte FRAM . |
Darn the small b, I was only off by a factor of 8
JovianPyx wrote: | I looked up the FM25V01 part at Mouser which lists it at $6.03 each for quantities of 10 |
That's really expensive for the density. I"m glad the instructor was able to get us samples. _________________ Free Tibet. Release the Panchen Lama from prison. Let the Dalai Lama return to his home. |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Fri Dec 07, 2012 5:45 pm Post subject:
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Yeah, that small b is for bITCH...
I hate that... _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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cappy2112
Joined: Dec 24, 2004 Posts: 2465 Location: San Jose, California
Audio files: 2
G2 patch files: 1
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Posted: Fri Dec 07, 2012 8:41 pm Post subject:
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JovianPyx wrote: | Yeah, that small b is for bITCH...
I hate that... |
_________________ Free Tibet. Release the Panchen Lama from prison. Let the Dalai Lama return to his home. |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Sat Dec 08, 2012 10:59 am Post subject:
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A note about the 23A1024 128 kilobyte SPI SRAM - this is a low voltage part, Vcc should be 2.2 volts.
23LC1024 is the same size RAM, but allows Vcc voltages between 2.5 and 5.5 volts. I need it for 3.3v... _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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yogi
Joined: Jun 26, 2008 Posts: 29 Location: Maryland
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Posted: Tue Jan 15, 2013 10:49 am Post subject:
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Thank you. Beatuiful timing; 2/3rds of the way with a dsPIC board build and have some 'LC1024s in the FedEx pipeline |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Tue Jan 15, 2013 5:48 pm Post subject:
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I have now soldered the 23LC1024 device into the board. I have set pin 3 to Vcc (reading AN1484 from Microchip). I modified the diagnostic and of course it doesn't work. I looked at the output with an oscope (SO pin on the SRAM chip) and it wasn't toggling, then I unsoldered the dsPIC pin from it so I'm seeing just the data coming from the SRAM chip and it's always low. I can see 5 bursts of 8 clock pulses, so that part is working (at least I get the 40 clocks required).
Now I am going to try another program that just repeatedly reads the mode register. Hopefully, that leads me to the problem.
So - anyone else have success with their 23LC1024 on a dsPIC? _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Wed Jan 16, 2013 4:37 pm Post subject:
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Still getting no love from the 23LC1024.
I've written a simple program to write and read the mode register and I get zeros for data. To make sure that the dsPIC pin receiving data from the SRAM is not holding it at ground, I removed the wire and scoped SRAM pin 2, stays at ground.
I can see clocks and I can see data, both pins toggle between Vcc and Vss.
Scoping SRAM pin 2 I see Vss all the time...
I keep thinking I should replace the SRAM chip. I have another free sample.
Ok - I just tried piggy backing the old 23K256 except for pins 2 and 3. 23K256 pin 2 toggles, 23LC1024 pin stays at ground (Vss).
Here is the program:
Code: | ;
; Project: hello world test for Effects boards
;
; Description: This is a test program that simply reads the 23LC1024
; mode register and displays the contents as hex. It is
; meant to troubleshoot a problem where there appears to
; be no data coming from the SRAM's SPI SO pin (pin 2).
;
; SPI SRAM uses pin 15 (RB6) to operate ~CS pin.
; UART1 uses Pin 21 RP10 as output.
;
; read mode register command byte: 0x05
;
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;Sec 0.0. Processor Setup
;------------------------------------------------------------------------------
.equ __33F128GP802, 1
.include "p33FJ128GP802.inc"
;------------------------------------------------------------------------------
;Sec 0.1.Configuration Fuses
;------------------------------------------------------------------------------
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; These settings were given to me by Tom Wiltshire:
; Without code to set PLL, this runs at 32 MIPS.
config __FGS, GSS_OFF & GCP_OFF & GWRP_OFF ; Code Protection
config __FOSCSEL, FNOSC_PRIPLL & IESO_ON ; Oscillator (20MHz ext Xtal) with 2 speed start-up
config __FOSC, FCKSM_CSDCMD & IOL1WAY_OFF & OSCIOFNC_OFF & POSCMD_HS ; Oscillator (20MHz ext Xtal) with 2 speed start-up
config __FWDT, FWDTEN_OFF & WINDIS_OFF ; Watchdog
config __FPOR, ALTI2C_ON & FPWRT_PWR16 ; Power up options (16ms)
; for debugging
config __FICD, ICS_PGD1 & JTAGEN_OFF
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;Sec 0.2.Global Equates & Symbols
;------------------------------------------------------------------------------
.equiv LED, 4 ; there is a LED on PORTA, #4
;------------------------------------------------------------------------------
;Sec 0.3.Global Declarations
;------------------------------------------------------------------------------
.global __reset
;------------------------------------------------------------------------------
;Sec 0.4.Global Initialised Variables
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;Sec 1.0.Main Code
;------------------------------------------------------------------------------
.section .text
__reset:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; *** IMPORTANT ***
;
; THE FOLLOWING INSTRUCTION SEQUENCE WORKS TO PLACE THE dsPIC INTO HSPLL MODE
; RUNNING AT 40 MIPS. HOWEVER, IT WILL NOT RUN AFTER A PROGRAM OPERATION BY
; JUST SETTING MCLR TO Vdd. YOU MUST POWER CYCLE TO START THE PROCESSOR.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; From Tom Wiltshire - to get dsPIC running at 40 MIPS with 20 MHz xtal
;.....................................................................
; Set up Oscillator, PLL, DAC and all Pre/Postscalers
; We use the HS osc with external 20MHz crystal
;.....................................................................
; Code required for 40 MIPS. If this is commented, it runs at 32 MIPS
MOV #0x0002, W0
MOV W0, CLKDIV
MOV #0x001E, W0
MOV W0, PLLFBD
; HS Osc with Xtal = 20MHz
; PLL Prescaler (N1) = /4 = 5MHz
; PLL Multiplier = x32 = 160MHz (Fvco)
; PLL Postscaler(N2) = /2 = 80MHz (Fosc, for an Fcy of 40MHz)
; Fvco is used as ACLK = 160MHz
; DAC Prescaler = /7 = 22.8MHz DAC Clock division /256 = 89.285 KHz sample output rate
; Clocks per DAC update = 448
; DAC Prescaler = /8 = 20.0MHz DAC Clock division /256 = 78.125 KHz sample output rate
; Clocks per DAC update = 512
;
; Disable auxillary oscillator and use primary osc instead
MOV #0x0780, W0
MOV W0, ACLKCON
; Aux Clk divide = /1
; Primary osc is aux clock source
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; test oscillator LOCK bit
PLL_lock_test:
BTST OSCCON, #LOCK
BRA Z, PLL_lock_test
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Set stack pointer and stack limit
MOV #__SP_init, W15 ; Initialize the Stack Pointer
MOV #__SPLIM_init, W0 ; Initialize the Stack Pointer Limit Register
MOV W0, SPLIM
NOP ; Add NOP to follow SPLIM initialization
; SPI 1, operates in 3 pin mode (SDI, SDO and SCK). The SRAM IC is expected to be always chip-selected.
; RPINR21<4> SS1R<4> = 11111 : (tied to Vss)
; pin 16 SDI RP7 RPINR20<4> SDI1R<4> = 00111 : Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits
; pin 17 SCK RP8 ???--> RPOR4<4> RP8R<4> = 01000 : for SCK1OUT 01000 RPn tied to SPI1 Clock Output
; pin 18 SDO RP9 ???--> RPOR3<4> RP6R<4> = 00111 : for SDO1 00111 RPn tied to SPI1 Data Output (SDO1)
; NOTE: SDI IS NOT USED IN THE MIDI CONTROLLER
BSET TRISB, #RB7 ; pin is input (SDI)
BCLR TRISB, #RB8 ; pin is output (SPI clock)
BCLR TRISB, #RB9 ; pin is output (SDO)
MOV #0x001F, W0
MOV W0, RPINR21 ; tie SS high
MOV #0x0007, W0
MOV W0, RPINR20 ; SDI is input on RP7 pin 16
MOV #0x0708, W0 ; set both RP9 (high byte) and RP8 (low byte)
MOV W0, RPOR4 ; SDO is output on RP9 pin 18, SCK is output on RP8 pin 17
CLR SPI1CON2 ; disable SPI frames
; SPI clock
; MOV #0x0000, W0 ; slowest clock setting (for testing)
MOV #0x0001, W0 ; 8:1, 16:1 312.5 KHz
; MOV #0x0002, W0 ; 8:1, 4:1 1.25 MHz
; MOV #0x0012, W0 ; 4:1, 4:1 timer 0x0040 2.50 MHz
; MOV #0x001A, W0 ; 2:1, 4:1 timer 0x0020 5.00 MHz
; MOV #0x001E, W0 ; 1:1, 4:1 timer 0x0010 10.00 MHz
MOV W0, SPI1CON1
BCLR SPI1CON1, #DISSCK ; disable clock pin not set
BCLR SPI1CON1, #DISSDO ; disable output pin not set
BCLR SPI1CON1, #MODE16 ; 16 bit mode not set.
BCLR SPI1CON1, #SMP ; 0 = Input data sampled at middle of data output time (for master mode)
BCLR SPI1CON1, #CKE ; 0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)
BCLR SPI1CON1, #SSEN ; 0 = SSx pin not used by module. Pin controlled by port function
BCLR SPI1CON1, #CKP ; 0 = Idle state for clock is a low level; active state is a high level
BSET SPI1CON1, #MSTEN ; set Master Mode Enable
BCLR SPI1STAT, #SPIROV ; clr Receive Overflow Flag
BSET SPI1STAT, #SPIEN ; set SPI Enable
NOP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Set up to use UART1 as TTY out 115.2 kbaud. Pin 21 RP10
MOV #0x0003, W0
MOV W0, RPOR5 ; move 0x0300 to RPOR5 [4:0] to assign RP10 to U1TX (pin 21). Value = 00011 (3)
MOV #0x0108, W0
MOV W0, U1MODE ; high speed, simplex, 8 bits, 1 stop bit
MOV #0x40C0, W0
MOV W0, U1STA ;
; 40 MIPS
; MOV #259, w0 ; 38.4 kbaud (hi speed. 9600 if low speed)
MOV #85, w0 ; 115.2 kbaud 86.805555555555555555555555555556 THIS WORKS
MOV w0, U1BRG
BSET U1MODE, #15 ; UART enable
BSET U1STA, #10 ; tx enable
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
BCLR TRISA, #TRISA4 ; use RA4 for an output for LED
BCLR TRISB, #6 ; Pin 15 (RB6) is used to operate ~CS line
BSET PORTB, #6 ; set RB6 high forcing ~CS high
BSET PORTB, #6 ; set ~CS high
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
loop:
BTG PORTA, #LED
; first write to the mode register
BCLR PORTB, #6 ; set ~CS low
NOP
NOP
MOV #0x01, W0 ; command = write mode register
CALL SPIwrite ; write the byte in W0 to SPI1
CALL SPIread ; satisfy read (terminates when data is ready, so we know operation is complete)
MOV #0x80, W0 ; data for mode register
CALL SPIwrite ; write the byte in W0 to SPI1
CALL SPIread ; satisfy read (terminates when data is ready, so we know operation is complete)
BSET PORTB, #6 ; set ~CS high
NOP
NOP
BCLR PORTB, #6 ; set ~CS low
NOP
NOP
MOV #0x0005, W0 ; read mode register command
CALL SPIwrite ; write the byte in W0 to SPI1
CALL SPIread ; satisfy read (terminates when data is ready, so we know operation is complete)
CLR W0
CALL SPIwrite ; write the byte in W0 to SPI1
CALL SPIread ; satisfy read (terminates when data is ready, so we know operation is complete)
NOP
NOP
BSET PORTB, #6 ; set ~CS high
GOTO loop
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Subroutines
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SPIread: ; wait for receive buffer full
BTST SPI1STAT, #SPIRBF ;
BRA Z, SPIread ; loop until full indication
MOV SPI1BUF, W14 ; get received data
RETURN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SPIwrite: ; write W0 to SPI.
BCLR SPI1STAT, #SPIROV ; clr Receive Overflow Flag (if set)
BTST SPI1STAT, #SPITBF ; test xmit buf full bit
BRA NZ, SPIwrite ; keep testing if set
MOV W0, SPI1BUF ; send the command to the SPI1 data reg to start the SPI byte write
SPIwrite1:
BTST SPI1STAT, #SPITBF ; test xmit buf full bit
BRA Z, SPIwrite1 ; keep testing until it sets.
RETURN
.end
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_________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Wed Jan 16, 2013 5:54 pm Post subject:
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I've replaced the 23LC1024 with a new one. It does the same thing as the other one. I'm out of free samples at this point. When a 23K256 is soldered in, there is toggling on it's pin 2. When a 23LC1024 is soldered in, there is no toggling of pin 2. The instructions for reading and writing the mode/status is the same for both ICs.
I'm using the code posted above. All it does is provide a "scope loop". there should be some toggling of the SO output from the SRAM.
I'm especially interested in experience with ICs that are not free samples. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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yogi
Joined: Jun 26, 2008 Posts: 29 Location: Maryland
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Posted: Wed Jan 16, 2013 6:20 pm Post subject:
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I haven't dug too deep into your code, mainly because it worked with the '256 and you made adjustments to the adr length. So I'm thinking you could have s slight difference between the two chips. I found a note in the 23xx1024 DS in Fig 3.8 that notes 3 Pin should not be left floating with Non-SQI operations.The text doesn't say a word about that and the pin diag shows it as NC. This is different then on the '256 where Pin 3 is a NC. Don't know if you made this change to you layout and don't know what happens if it IS floating but that's the only diff I can see so far. |
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