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 Forum index » DIY Hardware and Software » Microcontrollers and Programmable Logic
dsPICs, let's talk about them
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JovianPyx



Joined: Nov 20, 2007
Posts: 1221
Location: West Red Spot, Jupiter
Audio files: 157

PostPosted: Sat Jan 12, 2013 5:57 pm    Post subject: Reply with quote  Mark this post and the followings unread

Hmm. Wel I think I understand the question...

First, I've not used the DAC in DMA mode yet.

Second, my first and main experiences with DSP was in an FPGA. In that environment, the way the DAC is fed, it always gets fed new data at the designed sample rate. This is the way I would also approach a DSP problem using a CPU. Making the next sample available to the DAC when or before it needs it is the most important factor in the system.

If there is a chance that data can be late (that is, take too long to produce or there isn't enough headroom in the sample rate) then the target sample rate might be too high.

The dsPIC DACs operate from a 4 sample FIFO. There is also an emergency value register that is used when no data is available via the FIFO. This emergency register value is usually set to zero, but that's still going to insert a zero value that doesn't belong there and the result will probably not be "pretty music".

If you have a system that has variability, you want to set your sample rate to deal with the slowest it will ever be. If the rate could vary from say 50 khz to 70 khz, I'd set the sample rate at 50 khz or slower.

If the actual rate stays constant, then the output will be true to the number stream. This is always a good thing. It's better to have to deal with a slow, but constant sample rate than to consider that sometimes samples might not be there in time. Remember too about the nyquist limit. If you update slower than the sample rate then your nyquist limit goes down too and you have the opportunity for alias image artifacts.

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yogi



Joined: Jun 26, 2008
Posts: 25
Location: Maryland

PostPosted: Sat Jan 12, 2013 8:37 pm    Post subject: Reply with quote  Mark this post and the followings unread

Very insightful. The few threads I read, had differing reports on the noise floor for the DAC, some were experiencing high levels while others found no problems. I can see that noise can easily be introduce by bad design rather then a hardware defect. For synth apps there is more control, but dealing with slow memories, Audio over USB and such for playback could pose blocking problems.
From my (beginning) studies, using DMA seems an extremely powerful approach. In effect, expanding the DAC's FIFO. As long as the system can keep up with servicing the DPRAM, the DAC shouldn't 'run dry'.
Thanks
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