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Good Audio FPGA Development Board Candidate
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JovianPyx



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PostPosted: Wed Oct 09, 2013 12:40 pm    Post subject: Good Audio FPGA Development Board Candidate Reply with quote  Mark this post and the followings unread

http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1198&Prod=ZYBO

The ZyBo is still in pre-order, but the price from Digilent is $149. Generally, the board has:
512 MB DDR3 SDRAM
Zynq FPGA IC (which contains 2 onchip ARM cores each capable of running up to 667 MHz)
Audio Codec (audio connectors on board - though output is labeled headphones)
USB
Ethernet
HDMI
VGA.
5 PMOD sockets (each is a dual really, 12 conductors with 8 for signals)

All I would need is one pin on one PMOD for MIDI input and I'm good to go.

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Last edited by JovianPyx on Sat Feb 15, 2014 7:51 am; edited 1 time in total
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Dan Lavin



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PostPosted: Wed Oct 09, 2013 1:27 pm    Post subject: Reply with quote  Mark this post and the followings unread

nice find, Scott. Nice size for the board, too. Would you still want midi if you have usb? Or do you feel that would drag you down?
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JovianPyx



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PostPosted: Wed Oct 09, 2013 1:38 pm    Post subject: Reply with quote  Mark this post and the followings unread

Well, certainly we can use USB to receive a MIDI data stream and I may do that with special programs I write for a PC. In fact, I've done that with one synth and an Aleatoric Sequence Generator (a big nasty VB.NET program).

But I also have a number of hardware MIDI synths that use the standard 5 pin DIN and when I'm creating a piece that uses those other hardware devices with a PC based sequencer, I need to use the 5 pin DIN. The electronics for the interface are so inexpensive it's not worth mentioning the price. In fact, I've already got a PMOD board with the MIDI current loop electronics that will plug into one of the PMOD connectors.

But that's the real beauty of an FPGA - we can just substitute the modules we need. There is ethernet on the board and I'd bet usable/modifiable cores and then one could have MIDI over ethernet.

The problem I have with using USB for transmitting MIDI data streams is that I have no software that supports it on the PC side. That is, software that includes a well featured sequencer. For that I use Cakewalk (an ancient version that runs on a win98SE box). Educate me if I am wrong, but is it not true that things that can use USB for MIDI must see the USB port as a MIDI port and not a COM port? I have a feeling that this FPGA board will show up as some COM port when the driver is loaded and the bridge is setup (assuming there is a bridge).

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cbm



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PostPosted: Thu Oct 10, 2013 2:24 am    Post subject: Reply with quote  Mark this post and the followings unread

How much are the development tools for a mixed system like this?
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PostPosted: Thu Oct 10, 2013 5:27 am    Post subject: Reply with quote  Mark this post and the followings unread

There is a free version of Vivado that supports the FPGA. I've not used it, but I know it's a different sort of work flow from ISE (which I have used).
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anigbrowl



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PostPosted: Sun Oct 20, 2013 4:33 pm    Post subject: Reply with quote  Mark this post and the followings unread

This looks really cool and more flexible than the Mojo boards (also cool, but the tutorials seem uber-basic).

I'm having some conceptual trouble in figuring out how one goes from digital logic to audio processing. I'm broadly familiar with DSP and have some experience with Motorola/Freescale 56k assembler (long ago). what I'm specifically interested in is FX processing rather than pure synthesis, and I'm particulary implemented in reimplementing Dattoro's classic algorithms as found in the Ensoniq ESP2 chip. I've spent some time looking at Scott's project pages and source files, but (to put it in a nutshell) I'm not seeing what's better about implementing in an FPGA vs a regular DSP chip. Or rather, I'm not seeing that it's any easier from the development POV - obviously it would allow me to reimlement the EDP2 chip if I were bent on doing that.

Am I looking in the wrong place? I'm trying to find examples that are just slightly above 'Hello Word', eg adding some gain to a signal or summing two signals or other very basic DSP operations. Sorry for asking such an obvious question, but the FPGA Synth Wiki seems to go from LED-blinking Hellow World examples straight into phase distortion oscillators.

Putting the question another way, suppose I have a DSP algorithm chart, what is my workflow for changing this into a digital circuit?
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JovianPyx



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PostPosted: Sun Oct 20, 2013 7:05 pm    Post subject: Reply with quote  Mark this post and the followings unread

To me, whether you do DSP in a DSP chip or a FPGA is the same exercise. Different languages, but the processes are the same. We need to create a new sample before the sample clock ticks over.

In my view, if you are more comfortable with a specific DSP device, then use that. An FPGA is not a DSP device specifically, though it can be used that way. Some of the newer ones do have built in DSP accereration hardware, but again, these devices are also not specifically DSP. And I believe that if you wanted a contest between "best FPGA" and "best DSP" for a DSP job, you'd probably find DSP ICs that would be faster or better in some way or other. The strength an FPGA has is parallelism. If you can take advantage of that, then an FPGA can be the better platform.

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anigbrowl



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PostPosted: Sun Oct 20, 2013 10:11 pm    Post subject: Reply with quote  Mark this post and the followings unread

Thanks for that remarkably clear answer. I have the full chip specification for the ESP2 and it would be a fascinating intellectual exercise to re-implement it on FPGA but ultimately I'm interested in it because I'm a fan of Dattoro's algorithms.
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PostPosted: Sun Oct 27, 2013 2:23 pm    Post subject: Reply with quote  Mark this post and the followings unread

Concerning the free version of Vivado, you have to have WebTalk enabled for it to work:

13. WebTalk Notice, Consent and Opt-Out.

(a) Collection and Transmission of Data. "WebTalk" is a feature of the Software that electronically transmits to Xilinx various data relating to Licensee's use of the Software. WebTalk does not transmit the actual logic designs or Bitstreams processed via the Software. The types of data that WebTalk will transmit to Xilinx include: (i) constraint data (e.g., location assignments, clock and timing requirement and assignments, any constraints set via the Software graphical user interface), (ii) device data (e.g., targeted device and family), (iii) compilation data (e.g., device, memory and I/O utilization, time of compilation), (iv) design data (e.g., the number of each type of file used, intellectual property cores/LogiCORE IP cores logic functions used, and intellectual property parameterization), (v) Software data (e.g., synthesis, simulation and timing analysis tools used, and version and build of the Software), (vi) platform data (e.g., operating system, speed and number of processors and main memory), (vii) Authorization Codes data, (viii) Software errors log data (e.g., previous exit status), and (ix) help access data. Xilinx may correlate the data collected by WebTalk (primarily via the Authorization Codes data) to determine the identity of the Licensee and the User. WebTalk functions by bundling the collected data resulting from your use of the Software and writing it to html and/or xml files which are electronically transmitted over the internet to Xilinx by https (hypertext transfer protocol secure) post. WebTalk collects and maintains the last usage_statistics_webtalk file that was meant for transmission for a given design. Every new re-compilation of that given design will overwrite the previous file. If the https post transmission fails, or an internet connection is not available at the time of attempted transmission, the data is stored as an html and/or xml file. Once an internet connection is achieved by Licensee, the https post transmission will again be attempted upon re-compilation. The operation of WebTalk will not materially affect the performance of the Software.

(b) Use, Protection and Disclosure of Data. Xilinx uses the data received via WebTalk so that Xilinx can continuously improve the Software and other products, technologies and services that Xilinx offers to its customers, and also for sales and marketing email communications (for example, for selective announcement of new Xilinx products and services, distribution of marketing data, etc.). Xilinx uses reasonable efforts to maintain the privacy of the data during transmission (as discussed above) and after receipt by Xilinx via "firewalls" and other commonly available physical and technical security measures. However, due to technological limitations, the transmission of data through various internet service providers not under contract with Xilinx, and the risk of unlawful interceptions and accessing of transmissions and/or data, Xilinx cannot completely assure Licensee or Users, and Licensee and Users should not expect, that the data will be absolutely protected or confidential. If you attempt to tamper with or modify the Software in any way (other than as expressly authorized by Xilinx in this Agreement), Xilinx disclaims all responsibility for the operation of WebTalk and for the collection, transmission and protection of data as described herein. Xilinx may disclose data received via WebTalk to its corporate subsidiaries and to its authorized distributors and sales representatives (collectively, "Sales Partners"), which disclosures may be in a form that may be correlated to personally identify Licensee and Users, for their use of such data in the same manner as Xilinx might use such data. Except for disclosures to its Sales Partners, the data received by Xilinx via WebTalk will not be intentionally disclosed by Xilinx to any third parties in a form that is knowingly capable of being correlated to personally identify Licensee and its Users; however, Xilinx may share this data in an aggregate form that does not knowingly identify Licensee and its Users with its business affiliates including without limitation electronic design automation (EDA) companies with whom Xilinx has a commercial relationship including, but not limited to, Synopsys, Mentor Graphics, and Cadence. Xilinx also seeks to require Sales Partners and business affiliates to exercise reasonable efforts to maintain the confidentiality of the data disclosed to them. In addition to disclosures to Sales Partners, Xilinx may disclose personally identifiable data (collected by WebTalk and correlated to Licensee and Users), with or without prior notice, when Xilinx believes that the law requires it, in response to subpoenas or at the demand of governmental agencies, to protect its systems or business, or to respond to an emergency. Further, Xilinx reserves the right to transfer any and all data collected by WebTalk from Licensee and Users to a third party in the event that Xilinx sells or transfers substantially all of its assets related to the Software to such third party.

(c) Enable/Disable. Please note that WebTalk will collect and transmit certain data that may contain (or be correlated to reveal, primarily via the Authorization Codes data) personally identifiable information. By agreeing to this Agreement, you hereby give your consent (on behalf of Licensee and Users) for Xilinx to use and disclose this information anywhere in the world for the purposes and as described in this Agreement. Licensee or its Users may disable/enable WebTalk during installation or by editing the user preferences in Project Navigator, iMPACT, Vivado or PlanAhead or by running the xwebtalk command line utility which is located in your ise/bin/<os> folder, where os is nt, nt64, lin or lin64. Please note that WebTalk data transmission is mandatory for ISE WebPACK and Vivado WebPACK software (which are made available by Xilinx at no charge) and for alpha, beta or similar early access versions of Xilinx software products, and WebTalk makes decisions on data transmission based on the Authorization Codes used for design compilation; the only exception to this mandatory transmission is if the software is used on a machine that is not connected to the internet. If you obtained ISE WebPACK or Vivado WebPACk software (which are made available by Xilinx at no charge) and desire to have the ability to disable WebTalk, you may purchase a license to another version of the Software and not use the ISE WebPACK or Vivado WebPACK software. Versions of the Software for which Xilinx is paid a license fee contain the capability for disabling WebTalk as described herein.



The important bit is:

Please note that WebTalk will collect and transmit certain data that may contain (or be correlated to reveal, primarily via the Authorization Codes data) personally identifiable information. By agreeing to this Agreement, you hereby give your consent (on behalf of Licensee and Users) for Xilinx to use and disclose this information anywhere in the world for the purposes and as described in this Agreement.



I didn't install it!
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anigbrowl



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PostPosted: Sat Nov 02, 2013 12:57 pm    Post subject: Reply with quote  Mark this post and the followings unread

Meh, they're not claiming ownership of your IP. I got a call from the marketing department of Cypress (PSOC) but they just wanted to know what sort of things I thought their chip would be good for, how many units a commercial product of that kind might sell, what was my level of experience etc. I don't think you ought to be concerned about if you don't have a bunch of capital invested in product development/IP.
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BobTheDog



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PostPosted: Sat Nov 02, 2013 1:11 pm    Post subject: Reply with quote  Mark this post and the followings unread

I wasn't worried about ip, I was worried about the fact they are quite willing to share my registration details with whoever they want.
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State Machine
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PostPosted: Thu Dec 19, 2013 11:34 am    Post subject: Reply with quote  Mark this post and the followings unread

Here is a link to training videos for the Zynq 7000 series if anyone is interested.

http://www.xilinx.com/training/zynq/index.htm

Bill
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JovianPyx



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PostPosted: Fri Feb 14, 2014 3:36 pm    Post subject: Reply with quote  Mark this post and the followings unread

My ZyBo board arrived today.

There are only 2 documents I was able to find on www.digilentinc.com, those are a schematic and a features document. I will download the Xilinx Zynq chip docs from the Xilinx site.

The Digilent site says (in the product description) that there is a linux distro that will run on it. From the small amount of the docs I've looked at, it appears the it can boot from a microSD card (which I need to get). There may be other ways to boot it as well.

I have a feeling that this will take a few days to get "hello-world" stuff running, but it should be fun and it will keep me off the streets.

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JovianPyx



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PostPosted: Sat Feb 15, 2014 8:03 pm    Post subject: Reply with quote  Mark this post and the followings unread

These http://www.xilinx.com/training/zynq/index.htm videos that Bill recommended are quite good.

I wish the entire set were available tho and hopefully the rest will appear soon.

The last 5 of the first set of 13 would be some of the most interesting to me.

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State Machine
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PostPosted: Sun Feb 16, 2014 7:46 am    Post subject: Reply with quote  Mark this post and the followings unread

I agree, the videos are very well done. Despite the fact that the processing system can be tightly coupled to the programmable logic, however , it can be run independently from the programmable logic block so maybe just getting some "hello world" stuff may not be as far away as you might think. It should be interesting how well the Vivado design environment and flow works with the development board you purchased Scott.

I have not downloaded the Vivado design suite yet nor have I worked with it so I suppose you will be our testing ground Wink

Bill
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JovianPyx



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PostPosted: Sun Feb 16, 2014 8:28 am    Post subject: Reply with quote  Mark this post and the followings unread

Oh yes, and that was one of the things pointed out in the videos - you don't need to use either of the ARM cores if you don't need them.

Though when I see those two juicy 650 MHz 32 bit ARM cores (with floating point), I start to think about how I can make an instrument using those as well as FPGA fabric for accelerator logic. I think that just one of those ARM cores all by itself would probably make a nice synth.

Anyway, I need to scrounge up a USB cable since nothing but the board comes with the order. It's a standard type USB cable, nothing special about it for programming the board.

I'll probably start out with ISE 14.x since that is required at minimum. Just a LED blinker... I don't know if ISE can deal with the ARM cores at all, I'll find out though. ISE is probably messier than Vivado. I've downloaded the installer, but haven't yet run it.

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PostPosted: Sun Feb 16, 2014 10:33 am    Post subject: Reply with quote  Mark this post and the followings unread

Well, this is going pretty much as usual...

I've started a project in ISE 14.6 which supports the zynq 7010 IC. However, with ISE, one needs a UCF file to connect IC pins to named resources that will be used in the design. So far, I can't find a "master UCF file" that describes all of the board's connections.

Some of the search hits indicate that UCF is now obsolete for Vivado - but I'm not using Vivado yet and ISE requires the file. I may have to try Vivado if I can't get anywhere with ISE 14.6.

Of course, if anyone out there knows where I can find the master UCF, I'd be eternally grateful.

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PostPosted: Sun Feb 16, 2014 3:39 pm    Post subject: Reply with quote  Mark this post and the followings unread

Scott,

Perhaps Digilent, the distributer of the Zybo, may have a master UCF file? You may want to contact their support. There are no reference or example projects for the board?

Bill
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JovianPyx



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PostPosted: Sun Feb 16, 2014 3:55 pm    Post subject: Reply with quote  Mark this post and the followings unread

Well, Digilent is responsible for creating a master UCF - they have it for other boards, but I think this one being so new has some details yet to be finished. Another thing that is missing is the file package required for creating the linux boot on the micro-SD card. Their documentation says that they will be the supplier of that. Not sure why the UCF and the linux files aren't there yet - I would have thought that those are required to do the testing that I hope they did. I'd have appreciated at least a UCF so that I can play with the FPGA without the ARMs for now. I've not looked for reference designs yet, I don't have the USB cable to power/program it yet anyway...
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PostPosted: Mon Feb 17, 2014 7:02 am    Post subject: Reply with quote  Mark this post and the followings unread

I borrowed a USB micro B cable from my son and was able to run the demo stored in the QSPI flash. Stored there is a tiny bootable Linux. When I plugged the cable in, the board looked like it was doing something with activity on the USB LEDs. So I looked at the ports and there was a COM port that wasn't there before. I ran hyperterminal and connected to the port at 115.2 kbaud, 8 bits, 1 stop, no flow control and I got a ZyBo> prompt. I can see that telnetd, ftpd and httpd daemons are running. The Linux file system as booted consumes about 4.6 megabytes of DDR3 SDRAM. Within 'top' I can see that about 25 megs are used when Linux is running. There are also two commands for playing with LEDs and slide switches. write_led 0xNN writes the bits of NN to the LEDs (0x0F turns them all on) and read_sw reads and displays the 4 bit number represented by the slide switches. There is a tiny web server (httpd) that I was able to connect to with Firefox. I also used FTP to copy a jpg image to the server, I used vi to edit index.html so that it would display the image and that worked too. I had to dig around to change the IP address from it's default of 192.168.1.10 to 192.168.0.10. I used the command ifcfg to reconfigure the network interface.

All in all, it was a good day, I can see that the board works.

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PostPosted: Mon Feb 17, 2014 8:00 am    Post subject: Reply with quote  Mark this post and the followings unread

I've snagged a copy of dmesg output and it shows that this Linux is running on both ARM cores.

Code:

Booting Linux on physical CPU 0x0
Linux version 3.10.0-xilinx-14974-gb286654-dirty (Sham@TheFootball) (gcc version 4.6.1 (Sourcery CodeBench Lite 2011.09-50) ) #12 SMP PREEMPT Tue Nov 5 21:58:53 PST 2013
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Xilinx Zynq Platform, model: Xilinx Zynq Platform
bootconsole [earlycon0] enabled
cma: CMA: reserved 16 MiB at 1e400000
Memory policy: ECC disabled, Data cache writealloc
On node 0 totalpages: 131072
free_area_init_node: node 0, pgdat c05b31c0, node_mem_map c05e9000
  Normal zone: 1024 pages used for memmap
  Normal zone: 0 pages reserved
  Normal zone: 131072 pages, LIFO batch:31
PERCPU: Embedded 8 pages/cpu @c09f0000 s8256 r8192 d16320 u32768
pcpu-alloc: s8256 r8192 d16320 u32768 alloc=8*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 130048
Kernel command line: console=ttyPS0,115200 root=/dev/ram rw earlyprintk
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 512MB = 512MB total
Memory: 493576k/493576k available, 30712k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    vmalloc : 0xe0800000 - 0xff000000   ( 488 MB)
    lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc055143c   (5414 kB)
      .init : 0xc0552000 - 0xc057d040   ( 173 kB)
      .data : 0xc057e000 - 0xc05bb8a0   ( 247 kB)
       .bss : 0xc05bb8a0 - 0xc05e88f4   ( 181 kB)
Preemptible hierarchical RCU implementation.
   Dump stacks of tasks blocking RCU-preempt GP.
   RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
NR_IRQS:16 nr_irqs:16 16
ps7-slcr mapped to e0802000
Zynq clock init
sched_clock: 16 bits at 52kHz, resolution 18904ns, wraps every 1238ms
ps7-ttc #0 at e0804000, irq=43
Console: colour dummy device 80x30
Calibrating delay loop... 1299.25 BogoMIPS (lpj=6496256)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0xc03d60b8 - 0xc03d6110
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x72360000, Cache size: 524288 B
CPU1: Booted secondary processor
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated (2598.50 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
xgpiops e000a000.ps7-gpio: gpio at 0xe000a000 mapped to 0xe080c000
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
bio: create slab <bio> at 0
GPIO IRQ not connected
XGpio: /amba@0/gpio@41200000: registered, base is 252
GPIO IRQ not connected
XGpio: /amba@0/gpio@41240000: registered, base is 248
GPIO IRQ not connected
XGpio: /amba@0/gpio@41220000: registered, base is 244
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti>
PTP clock support registered
EDAC MC: Ver: 3.0.0
Switching to clocksource ttc_clocksource
NET: Registered protocol family 2
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP: reno registered
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 0 bytes, default 64
Trying to unpack rootfs image as initramfs...
rootfs image is not initramfs (no cpio magic); looks like an initrd
Freeing initrd memory: 3604K (df7cf000 - dfb54000)
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
msgmni has been set to 1003
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
dma-pl330: probe of f8003000.ps7-dma failed with error -2
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 82) is a xuartps
console [ttyPS0] enabled, bootconsole disabled
xdevcfg f8007000.ps7-dev-cfg: ioremap 0xf8007000 to e081c000
brd: module loaded
loop: module loaded
xqspips e000d000.ps7-qspi: master is unqueued, this is deprecated
m25p80 spi0.0: s25fl129p1 (16384 Kbytes)
4 ofpart partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000110000 : "qspi-fsbl-uboot"
0x000000110000-0x000000120000 : "qspi-devicetree"
0x000000120000-0x000000420000 : "qspi-linux"
0x000000420000-0x000000800000 : "qspi-ramdisk"
xqspips e000d000.ps7-qspi: at 0xE000D000 mapped to 0xE081E000, irq=51
e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
libphy: XEMACPS mii bus: probed
xemacps e000b000.ps7-ethernet: invalid address, use assigned
xemacps e000b000.ps7-ethernet: MAC updated 12:46:45:33:9c:3b
xemacps e000b000.ps7-ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
ULPI transceiver vendor/product ID 0x0424/0x0007
Found SMSC USB3320 ULPI transceiver.
ULPI integrity check: passed.
xusbps-ehci xusbps-ehci.0: Xilinx PS USB EHCI Host Controller
xusbps-ehci xusbps-ehci.0: new USB bus registered, assigned bus number 1
xusbps-ehci xusbps-ehci.0: irq 53, io mem 0x00000000
xusbps-ehci xusbps-ehci.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
xadcps f8007100.ps7-xadc: enabled:   yes   reference:   external
zynq-edac f8006000.ps7-ddrc: ecc not enabled
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: SDHCI controller on e0100000.ps7-sdio [e0100000.ps7-sdio] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
TCP: cubic registered
NET: Registered protocol family 17
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
Registering SWP/SWPB emulation handler
drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
RAMDISK: gzip image found at block 0
EXT2-fs (ram0): warning: mounting unchecked fs, running e2fsck is recommended
VFS: Mounted root (ext2 filesystem) on device 1:0.
devtmpfs: mounted
Freeing unused kernel memory: 172K (c0552000 - c057d000)
xemacps e000b000.ps7-ethernet: Set clk to 25000000 Hz
xemacps e000b000.ps7-ethernet: link up (100/FULL)
xemacps e000b000.ps7-ethernet: Set clk to 25000000 Hz
xemacps e000b000.ps7-ethernet: link up (100/FULL)

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State Machine
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PostPosted: Mon Feb 17, 2014 8:58 am    Post subject: Reply with quote  Mark this post and the followings unread

Wow, fantastic news !!! I can see from the "TTY" ports output that Linux is loading many of the usual suspects ! You can also try a SSH session with Putty and wee if that service is running. It usually is in Linux. May ask you for PW's.

Did you see if a video adapter block was created and enabled? Check for output on your HDMI or VGA ports ...

In any event, it's ALIVE !

Bill
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Audio files: 158

PostPosted: Mon Feb 17, 2014 9:27 am    Post subject: Reply with quote  Mark this post and the followings unread

State Machine wrote:
Wow, fantastic news !!! I can see from the "TTY" ports output that Linux is loading many of the usual suspects ! You can also try a SSH session with Putty and wee if that service is running. It usually is in Linux. May ask you for PW's.

Did you see if a video adapter block was created and enabled? Check for output on your HDMI or VGA ports ...

In any event, it's ALIVE !

Bill


Yes, I noticed something about SSH as I rummaged through the file system. I think it's the dropbear process. Anyway, I did connect using SSH and yes it asks for a username and password. Since the only account configured (as far as I can tell) is root, I entered root as the username. Then since I had no documentation to work with, I thought ZyBo, Xilinx, Digilent and Zynq might be passwords - all failed. So I guessed 'root' for the password - and that worked!

There was also something about video in my rummaging, so I will indeed (later today) try a VGA monitor (no HDMI equipment down here) and see if there's anything on it. There's no keyboard connector on the board, so I can't imagine what would be displayed there except maybe some hello-world sort of thing.

Looking in the bin subdirectory, there are some interesting command files including gzip and rpm. Apparently, this Linux seems derived from Red Hat - now I see why I feel comfortable in there... Heh - found sendmail... Most of the common command line utilities are there.

It's been great fun playing with this even in this minimal capacity. I've had to dust off my Linux command line skills. I've never had an embedded Linux system before, so this tiny Linux is a new experience and lots of fun. One of the best things about it is that I can do dangerous stuff in there and if I clown it up, I just power cycle and a few seconds later it's running again all healed.

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PostPosted: Wed Feb 19, 2014 1:46 pm    Post subject: Reply with quote  Mark this post and the followings unread

Two more files appeared on the Digilent site for the ZyBo. They are the master UCF file and the board description files needed by Vivado.

Today, I got those files and used the master UCF to build two small test designs. The first is a simple counting LED blinker using Verilog statements. The second is a cylon LED display using a PicoBlaze embedded microcontroller. Both work as expected. The PicoBlaze design was interesting because I started with a design for a Spartan-3A device. The old design used version 3 of PicoBlaze which was not prepared for the block RAMs that are in the Zynq. I found version 6, downloaded that and modified the source code to accomodate it. It's a little different, but the docs are good so not too hard to get it working. The new embedded processor is running with the system clock of 125 MHz. Version 6 is spec'd to be able to handle up to 240 MHz depending on the device. That is a significant boost in performance over version 3 which tops out at 50 MHz.

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FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.
Fruit flies when you're having fun.
BTW, Do these genes make my ass look fat?
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PostPosted: Wed Feb 19, 2014 8:07 pm    Post subject: Reply with quote  Mark this post and the followings unread

I hooked up a VGA monitor to the VGA port - the demo program in Flash does nothing with it.
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