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AlanP
Joined: Mar 11, 2014 Posts: 746 Location: New Zealand
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Posted: Tue Apr 25, 2017 9:29 pm Post subject:
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Can't really contribute anything, just posting to say that following this discussion has been both fascinating and also instructive |
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electrotech
Joined: Apr 24, 2013 Posts: 38 Location: Ayrshire Scotland
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Posted: Wed Apr 26, 2017 2:05 am Post subject:
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I posted my circuit suggestion above late last night and now having had another look at it, I realise that the rise and fall times might be too slow (~200ns) in order to reliably clock the counter... I should really get the prototyping board out and see if it works first !
So I now agree that this solution is probably better :-
PHOBoS wrote: | Instead of using 2 schmitt trigger inverters, which won't really help you, use a transistor (configured the same way as
Q5, Q6 in the original schematic but with a resistor to GND) followed by 1 schmitt trigger inverter. This will give you
a wider voltage range and because of the schmitt triggers smooth transitions at a logic level. Or, as I mentioned before,
some simple comparators which have always worked great for me.
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So, keep the input side as I posted above using a single 2N3904 but with just one 4k7 to 10k resistor for the collector load. This will take care of the voltage translation then feed the signal at the collector into the 40106 schmitt-trigger inverter to square things up nicely.
Andy
EDIT - I thought the rise/fall times were significant because I had problems getting the counter to work in my simulation software. However I've just done what I should have done in the first place and read the CD4029B datasheet... The maximum rise & fall times for the clock input are stated as 15μs so my circuit should work just fine. |
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blue hell
Site Admin
Joined: Apr 03, 2004 Posts: 24079 Location: The Netherlands, Enschede
Audio files: 278
G2 patch files: 320
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Posted: Wed Apr 26, 2017 2:53 am Post subject:
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Heh .. just looked that 15 µs up as well. _________________ Jan
also .. could someone please turn down the thermostat a bit.
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blue hell
Site Admin
Joined: Apr 03, 2004 Posts: 24079 Location: The Netherlands, Enschede
Audio files: 278
G2 patch files: 320
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Grumble
Joined: Nov 23, 2015 Posts: 1294 Location: Netherlands
Audio files: 30
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Posted: Wed Apr 26, 2017 4:02 am Post subject:
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Used to have that in my office... |
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elmegil
Joined: Mar 20, 2012 Posts: 2177 Location: Chicago
Audio files: 16
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Posted: Wed Apr 26, 2017 7:51 pm Post subject:
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electrotech wrote: | I posted my circuit suggestion above late last night and now having had another look at it, I realise that the rise and fall times might be too slow (~200ns) in order to reliably clock the counter... I should really get the prototyping board out and see if it works first !
So I now agree that this solution is probably better :-
PHOBoS wrote: | Instead of using 2 schmitt trigger inverters, which won't really help you, use a transistor (configured the same way as
Q5, Q6 in the original schematic but with a resistor to GND) followed by 1 schmitt trigger inverter. This will give you
a wider voltage range and because of the schmitt triggers smooth transitions at a logic level. Or, as I mentioned before,
some simple comparators which have always worked great for me.
|
So, keep the input side as I posted above using a single 2N3904 but with just one 4k7 to 10k resistor for the collector load. This will take care of the voltage translation then feed the signal at the collector into the 40106 schmitt-trigger inverter to square things up nicely.
Andy
EDIT - I thought the rise/fall times were significant because I had problems getting the counter to work in my simulation software. However I've just done what I should have done in the first place and read the CD4029B datasheet... The maximum rise & fall times for the clock input are stated as 15μs so my circuit should work just fine. |
Thank you very much Andy....
Your original circuit was very clear. The references here, however, confuse me. "so my circuit should work just fine", do you mean the original? Also, when you say "just one 4k7 to 10k resistor for the collector load" I'm not clear on what modification you intend for the original.
And then, going back to the original, the questions I have about that revolve around my poor grasp of the deeper workings of transistors.
1) how did you arrive at particular values? 4.7 & 2.2K in particular. I mean, it seems fairly obvious that 4.7 is a standard value roughly half 10K, and 2.2 is roughly half of 4.7K, but the ratios in general are opaque to me.
2) What is the advantage of using the NPN & PNP together rather than cascading NPN stages?
Thank you again, and I'm pleased once again to see that this place is much more educational for me than the constant roar in that other synth forum
P.S. Jan, thanks very much for the CMOS book link. I think I've had that on my book list for a while, but I was expecting I'd have to buy it..... so I hadn't yet. |
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elmegil
Joined: Mar 20, 2012 Posts: 2177 Location: Chicago
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elmegil
Joined: Mar 20, 2012 Posts: 2177 Location: Chicago
Audio files: 16
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Posted: Thu Apr 27, 2017 12:22 pm Post subject:
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(let's not discuss the ridiculously sized cap ) |
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electrotech
Joined: Apr 24, 2013 Posts: 38 Location: Ayrshire Scotland
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Posted: Thu Apr 27, 2017 1:04 pm Post subject:
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I've decided to build the clock interface circuit on a prototype board to make sure it works properly - however, this usually means that things like resistor values change because 'real life' circuits don't always behave like theoretical ones...
Once I've tried and tested it I'll post the results here, probably in a day or two.
The 'scope hasn't been powered up for a few months so the exercise will be good for it.
The biggest problem with bipolar transistors is actually switching them off once they're on, especially when they're 'saturated'. That's why I've got lowish value resistors between base and emitter - to help remove charge from the base region, but I'm sure that transistor theory isn't what you want to hear about !
Elmegil, when I came up with the NPN/PNP two-transistor circuit I didn't put that much thought into the precise values and just picked some that experience told me would be 'in the ball-park'. Turns out the two 4.7k's at the input were not optimal, in fact they load the voltage across the zener diode so much that the input would need to be more than 15V before it started to 'zener'... so I'll need to make some changes there.
The 2.2k in series with the 10k form a split-load resistor for the NPN transistor and act as a potential divider to reduce the bias voltage for the PNP transistor. This enables it to switch on and off cleanly.
You also asked about advantages of an NPN & PNP together rather than cascaded NPNs ?
Well, you save on one resistor for a start but also the switching times will be slightly different, but we're talking about one or two micro-seconds which I don't think would be noticeable !
Going back to your sequencer circuit, which I'm interested in making BTW, if you have a spare inverter gate in a 40106 then it makes sense to use it here, with a single NPN transistor in front of it for the voltage conversion.
I'll have a go at that too and will report back with some new circuits.
Andy
EDIT - Elmegil, you've beaten me to it !
I was typing the above when you made those posts.
I'm glad the circuit 'works' but could probably be improved... |
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gdavis
Joined: Feb 27, 2013 Posts: 359 Location: San Diego
Audio files: 1
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Posted: Thu Apr 27, 2017 1:27 pm Post subject:
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Just to add to what Andy wrote, choosing resistor values for circuits like this is usually a balance between static power dissipation and switching speed. Larger values will use less power but switch slower and vice versa.
There's a fair amount of leeway in DIY synths where you're not running at very high frequencies and not too concerned about minimizing power, though you do want to be reasonably mindful of these things. In higher performance applications these things become more critical (and a large part of the reason many things use CMOS instead of BJT's).
electrotech wrote: | Turns out the two 4.7k's at the input were not optimal, in fact they load the voltage across the zener diode so much that the input would need to be more than 15V before it started to 'zener'... |
Do you even need a zener here? Wouldn't a normal diode suffice since the input can go up to V+ without any harm?
elmegil wrote: |
Thank you again, and I'm pleased once again to see that this place is much more educational for me than the constant roar in that other synth forum
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OMG, thank goodness I'm not the only one!! _________________ My synth build blog: http://gndsynth.blogspot.com/ |
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electrotech
Joined: Apr 24, 2013 Posts: 38 Location: Ayrshire Scotland
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Posted: Thu Apr 27, 2017 1:43 pm Post subject:
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Correct, you don't actually need the zener with the circuit as it stands... a design error on my part.
So yes, an ordinary 1N4148 would get rid of negative voltages if present.
Andy |
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elmegil
Joined: Mar 20, 2012 Posts: 2177 Location: Chicago
Audio files: 16
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Posted: Thu Apr 27, 2017 3:41 pm Post subject:
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electrotech wrote: | EDIT - Elmegil, you've beaten me to it !
I was typing the above when you made those posts.
I'm glad the circuit 'works' but could probably be improved... |
Yah, probably, but you got me going
I did not, btw, do the following:
also put the same circuit in front of the reset input, which in fact is now not working for reasons I haven't gotten to yet. Still working out other stupid mistakes Like putting a 10K resistor in the "input" side of those 4051's, which made the other side turn into voltage dividers, oops.
use actual zeners -- I had the diode in the circuit already, and I'm not really going to be putting any stress on this iteration of the circuit. It will take a new PCB spin before I'm ready to actually exercise it seriously.
Also, I have no 40106 in the circuit currently, and after I realized I had to do run/stop (I keep forgetting....) I suddenly needed 7 inverters instead of 6, so I took it back out entirely. We'll see how layout looks, whether I think I can/should put one back in for some of the inverters..... |
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electrotech
Joined: Apr 24, 2013 Posts: 38 Location: Ayrshire Scotland
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Posted: Sun Apr 30, 2017 4:13 am Post subject:
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A bit late I know, but I've now tested the clock interface circuits on a breadboard and looked at the signals on the 'scope and have updated the circuit slightly. (shown below)
Both circuits give a 12V output when the input is above 3V and will withstand higher input levels without a problem.
Negative polarity signals are removed by the diode as already discussed.
Circuit 1
Since both transistors are switched ON when the input signal goes 'high' the response is very quick ( <300ns) so just what's needed for the counter chip. The output transition from ON to OFF is a bit slower though but I don't think that matters for this application.
Circuit 2 shows the simpler circuit that can be used if there is a spare inverter gate available.
This switches ON with a similar response time to Circuit 1 but the switch OFF time is much faster with very sharp rise and fall times.
Anyway, I hope this is of interest.
Andy
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Circuit1 NPN/PNP clock interface |
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Circuit 2 NPN plus Schmitt inverter clock interface |
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elmegil
Joined: Mar 20, 2012 Posts: 2177 Location: Chicago
Audio files: 16
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Posted: Tue May 02, 2017 11:27 pm Post subject:
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I just wish E-M would email me with updates. Those are great, thank you |
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droffset
Joined: Feb 02, 2009 Posts: 515 Location: London area
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elmegil
Joined: Mar 20, 2012 Posts: 2177 Location: Chicago
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Posted: Thu May 03, 2018 1:25 pm Post subject:
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So I've been fighting with the latest prototypes on this for a bit now.
I got past "skipping 0" every time, but now depending on the combination of rate and clock width, as well as the switch settings, I sometimes get a bounce at the start of a clock cycle. Blue line is pin 15 of the 4029. Yellow is in between the 1.2K and 10K resistors in the processing section. When I measure at the input to the processing section, I get a much slower slope, with a tiny little wiggle at the point of the glitch.
It occurs when one gate is off, and the next gate is on, at which point it skips the on step and goes on to the next one. If I go off -> off, I don't skip and if I go on -> on I don't skip. Faster clock speeds and wider gate lengths are less susceptible. Using an external clock from an MI Module Tester doesn't exhibit the problem. But I've looked at the clock I'm generating and it doesn't look like there's an issue, I don't see any glitches in that waveform (other than it being slow-ish.... hm...........)
All my chips are appropriately bypassed. There's not path that I can see between the switches and the counter -- all the switches are on the other side of 4051's. I've tried a few attempts to use flying wires to re-route traces incase there was trace interference, but nothing definitive (at one point I thought I had solved it, but then found changing the speed/width settings a little bit brought the problem right back).
My current operating hypothesis is that I need some kind of hysteresis in the processing section -- If I were using a 40106 or similar inverter, that would probably solve it. There's probably room on the PCB to put it, but it seems a waste for just a couple of gates.
Of course as I type this now I'm thinking about that slow clock (slow as in a few ms rise time....). The last buffer for the clock section is an LM358 I wonder if I'm just using a lousy amp for such purposes and ought to use something else for my pulse width modulator. Time to go read up on the slew rate of the LM358.
Curious if anyone else has any ideas.....
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elmegil
Joined: Mar 20, 2012 Posts: 2177 Location: Chicago
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elmegil
Joined: Mar 20, 2012 Posts: 2177 Location: Chicago
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elmegil
Joined: Mar 20, 2012 Posts: 2177 Location: Chicago
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