Delayed Design

[zipzap]

Hi Folks
I´ve got that stuff about a great delax unit in my head and i need some input from you guys. I have this old delay, half working, and it contains a ML3005. I want to build something out of that one day when that vco buisenes has ended and now i´m thinking of ways this unit could function.
I already learned from this forum : Design before delay!
Here´s what i already know:
VC time and feedback
pos and neg feedback + feedback insert
connects to mixing desk (1/4"in/out) and modular (bananadelay)
Aliasing filters with independant and delaytime-follow mode
Now i think about this stuff:
how about pingpong mode? As faar as i understand it takes some 4000 clock ticks for a sound that has entered the chip to come again. So if i got some device that can count up to those 4000 and turn a switch i got a pingpong delay. (If one side conts 12000 and the other 8000 i get something else)
Or maybe not a swich but two vcas. Then the 4000 counter can turn one vca off and the other on. And the vcas can also be used for ext cvs
Also i want some darth vader sounding mode.
This chip can go as slow as i want it to, right? At least if i cut the highs.
What do you think should a decent delay bring? Coffee?

[Mikmo]

If the 3005 IC works like other delays, the sound quality will go down, when you run i slower, i mean this thing i basically a "sampler" running it slower will reduce the sample speed and of course sound quality.

I build a delay based on the PT2399 IC. (the one at www.tonepad.com), i know it's different from the 300X IC's.

I substituted a much larger pot for the suggested delay time pot and i get much longer delays, but, the sound quality goes drastically down.

i'm a noise head, i like it that way, i also modified it so it has "endless repeats". So you have very long grainy noisy endlessly repeating echoes -
pure bliss

I have two more of the PT2399 IC's and i'm planning on using one for a delay like the one i have and set them op with "mutual feedback", the last one i wold like to use in a VC delay synth module, one day, when my "unfinished projects" pile is a little smaller....

[bugbrand]

Yeah, the PT2399s make incredible wierdy digi noise when slowed right right down (to something over 8 seconds delay).. Whooooah, really recommend them!

There's a Scott Bernardi design for PT2399

And you can get them pretty cheap off ebay - or Small Bear Electronics

[zipzap]

[zipzap]

Oh, and anybody know what happens if it´s not driven by a clock but by a fast pattern sequencer?

[Scott Stites]

[zipzap]

Hi scott, thanks for the info.
Yea, i belive it gets painful at 10khz already, but when cutting the highs with some steep slope (i´ve got some switched cab 24db ic somewhere that could follow the same clock) it should be possible. After all, if i want 5 minutes of clean delay i use a computer.
So if i want to drive it with a clock and buffer like you told me i would have to provide those vdd+1v myself. Is that critical for operation? Will a simple voltage divider work or is there actually current running? Those chips are hard to get by now and i don´t want to kill it...

[Scott Stites]

Hi ZipZap,

Yep - I PMed you an example. I'd hate for you to kill it too - those MN3005's are getting rarer (and more expensive) by the minute.

Right, if you filter it for slower clock frequencies, you'll be able to get rid of a lot of the clock whine. Audio signals will be a bit muffled, but the really slow clocks will sound pretty 'creaky' for want of a better word.

Cheers,
Scott

[zipzap]

Ok, in this case a 4047 is clocking directly with no buffers. What you are talking about is using opamp buffers for even higher frequencies, right?
Doepfer has the A188-1 BBD module. They say that the chip cannot be harmed by overclocking, but that results might not be as expected.
What is good, if i understood correctly, is that the bbd uses pos and neg edge for clocking. So the bbd of 10khz giving 204ms actually a 20khz clock is used, so freq. range is larger than i thought..

[Scott Stites]

Yes, not the greatest example when talking about buffers

I've seen re-workings of the circuit using 4041 buffers. STD-1 uses the 4041 buffer.

Cheers,
Scott

[zipzap]

I get the point about the buffer. I´ve got the datasheet for the 3005. Do you know why it has 2 outputs?
I found this file talking about max clock range. Looks like this chip can be clocked up to 200khz with two series resistors of 50ohm. So that must be flanger region.
It sais two 50 ohm resistors can cure the problem of high clock freqencies that is due to larger power consumpton. I attach it in case you haven´t got it (last page).
What i don´t understand is if those max 200mW are a problem for the 30xx chip or for the mn3101. I guess it´s because of the clock and therefor we are using those buffers.

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[Scott Stites]

There are two outputs because the buckets alternate between empty and full. If you just took the output of one string of buckets, your signal would be 'empty' half of the time. So, the second output puts out the same level that the first output had once the first output goes low and is getting ready to be filled again with the next sample.

I've attached a couple of illustrations from the SAD1024 data sheet to illustrate. The SAD1024 is a different model of BBD, but they're all functionally the same. Inside_bbd shows that the A' output (the "second" output) has an extra little stage there to feed the signal out when A (the first output) is empty. That way, you get a more-or-less constant output of the BBD.

BBD_output.jpg illustrates what the signal looks like on the respective outputs. The MN30XX datasheets rarely show them (they usually show fixed resistors), but a good idea is to put the outputs to each side of a trimpot and the center tap of the trimpot is the output to feed to the rest of your circuit. This allows one to null the clock signal as best as possible, rather than relying on the linearity of the device and fixed resistors. The MN320X datasheets invariably show this trimmer.

As an aside, the SAD1024 was a dual 512 stage device (like the MN3010) so that made it easy to set it up for parallel multiplex of two different BBD devices (in this case, both devices are in one package). This technique switches the clock signals around from one device to the next, and then it just mixes the same phase output of each device together. This allows the signal to change with each clock pulse, rather than spitting out a copy of the first output on the second output. This doubles the sample rate and allows double the resolution for the same delay time, or doubles the delay for the same sample rate. Using it to double the resolution of the same delay time doubles the Nyquist frequency, and, one assumes, would make one hell of a nice flanger setup.

I recommend the SAD1024 datasheet as a good source of BBD theory. You can get it here:

http://www.synthdiy.com/show/getfile.asp?get=882

Cheers,
Scott

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[StephenGiles]

Buffer the 4047 with a 4049 and get almost TZF with an SAD 1024!

[Yorky]

there are 2 clock feeds because these are in opposite phase because in the BBD every other bucket is empty at any one time, ready to be 'filled' be its neighbor. This is also why the equation for the delay time has a /2 in it

[StephenGiles]

http://img.photobucket.com/albums/v317/StephenGiles/ada_MI_1024.jpg

This is my redraw of the ADA Flanger - the MN3010 version, which Mike Irwin adapted for SAD 1024, with the 4049 buffer which allows rediculously high clocking!

[zipzap]

cool! yet another page to visit! Got some more stuff there?
http://img.photobucket.com/albums/v317/StephenGiles/
wants me to log in, so if there is more i can´t see that way.
cheers