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 Forum index » DIY Hardware and Software
9V Sample and hold
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mitch



Joined: Aug 28, 2005
Posts: 2
Location: SF

PostPosted: Sun Aug 28, 2005 4:25 pm    Post subject: 9V Sample and hold Reply with quote  Mark this post and the followings unread

I've been working on making a sample and hold circuit that will run on +9V. Here's a preliminary design.
Posted Image, might have been reduced in size. Click Image to view fullscreen.
This is not quite working yet. Sugestions greatly appreciated.
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Blue Hell
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Joined: Apr 03, 2004
Posts: 20681
Location: The Netherlands, Enschede
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PostPosted: Sun Aug 28, 2005 5:41 pm    Post subject: Reply with quote  Mark this post and the followings unread

Welcom to EM mitch.

I'm sory, but I had to delete your double posting. this one seemed most approriate to keep.

Here is some text that was in the other post but not in this one :
Quote:

This is not quite working yet. The LFO works and the noise source is working well. But the sample and hold section is quite working. If anyone has any suggestions or can point any glaring mistakes feel free, it will not hurt my feelings.

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dnny



Joined: Mar 12, 2005
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PostPosted: Mon Aug 29, 2005 12:29 am    Post subject: Reply with quote  Mark this post and the followings unread

i don´t know if this helps at all. but take a look at these sample and holds. there is good description how the circuits work -

so maybe youy will figure out whats wrong

S&H 2

Single Chip Simple Sample and Hold


daniel

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mitch



Joined: Aug 28, 2005
Posts: 2
Location: SF

PostPosted: Mon Aug 29, 2005 9:14 am    Post subject: Reply with quote  Mark this post and the followings unread

Thanks, I had seen these before but I felt there were too many parts and they include many extra features that do not need. These also run on a bipolar power supply.

Taking a second I look I might be able to borrow a few ideas.

If understand the how this works. It seems the important ideas are that the LFO needs to have high fast peak. The gate of the sample FET (Q1 in the case of the Single Chip Sample and Hold) needs to be at 0V when the LFO is low. The CV buffer (U1-b in the Single Chip Sample and Hold) must have insanely high input impedance, hence the use of TL-084 JFET op-amp.
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