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 Forum index » DIY Hardware and Software » Klee sequencer
Super Klee Sequencer
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Scott Stites
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PostPosted: Sat Sep 16, 2006 1:45 pm    Post subject: Reply with quote  Mark this post and the followings unread

Getting things to schematic now - I've got the gate bus on schematic and the clock input/control section as well as the encoder (though no random comparator function yet - the space on the schematic is allotted).

I've turned my attention to properly decoding the encoder - up to now, I've been coming straight off of the taps of the shift registers themselves - that means I've got an LED tied to ground through 4K7 and am also mixing them through pots to the simple mixer I've got on breadboard coming from each tap of the shift register. Works fine, but I'm going to armor-plate it, anyway.

The shift register taps will be buffered with CD4050s. The output of each buffer will drive an LED and send its high or low to the gate bus. Directly from the shift register, each bit will go to the control input of a CD4066 section. Feeding the CD4066 will be a selectable reference voltage, allowing one to set the range of control of the pots. The output of each 4066 will sum through a pot to the CV mixer. Feature creepily, a very cool function is the ability to adjust the reference voltage with a pot, or an external CV - a very cool effect one doesn't see in most, if any, sequencers. If, for example, you feed it a sine wave LFO, the output will be a Klee'ed, subdivided version of the LFO. Something to think about for model 3, I suppose. I think I can add skip, too, but that'll wait for model 3.

The above arrangement adds 3 4050s and 4 4066s.

As for the selectable range, I thought of a rotary switch that would select between 1, 2, 5 and 10V range (corresponding to 1, 2, 5 and 10 octaves of control). I dunno - 10 octaves sounds excessive - what do y'all think?

Cheerios,
Scott
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PostPosted: Sat Sep 16, 2006 1:48 pm    Post subject: Reply with quote  Mark this post and the followings unread

10 octaves is not excessive at all. Smile

edit; but being able to select would be very useful too Very Happy

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PostPosted: Sat Sep 16, 2006 1:53 pm    Post subject: Reply with quote  Mark this post and the followings unread

All righty, will do. In fact, a 10 position rotary would cover 1 to 10 octaves of control. I couldn't guarantee using CD4066s they'd jump exactly in those increments when switching from one to the other, but as a range select, it certianly would be handy.

Cheers,
Scott
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PostPosted: Sun Sep 17, 2006 11:22 am    Post subject: Reply with quote  Mark this post and the followings unread

Quote:
If it weren't for the stones we wouldn't know the difference.


Thanks again for that, Uncle K. I planted the comparator on the breadboard. I'd forgotten how much fun that function was. It's downstairs chirping and grunting like an Australian tree frog. The kind you lick Very Happy

Deviating from the original Klee, I'm using a Ken Stone comparator circuit on the front end (something Romeo did with his Klee).

I had an idea for a version of the Klee that would absolutely rock - the Klee Box. Use the gate bus from the Model 2, get rid of the 16 pots and put in 12 rotary switches.

Each Klee stage would have three rotary switches (four Klee stages).

One switch would choose from one of four bits to direct to the Klee stage. One switch would set the klee voltage in half step increments, the other switch would set the klee voltage in 1 octave increments. Put this in a box, with the LEDs and switches in a semi-circle above the Klee rotaries. This would make a very good performance box - no careful tuning required - one could flip rotaries on the fly. If one wanted something other than western scaling, each Klee stage could have an offset pot.

All after Model 2.

Cheerios,
Scott
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PostPosted: Sun Sep 17, 2006 2:40 pm    Post subject: Reply with quote  Mark this post and the followings unread

Well,
First of all. I don't know who told you that I lick frogs, but it's just not true! It was shown at the trial that there was absolutely no evidence of frog licking to be found! Well except for that silly woman with the bikini made of frog skin, but how was I to know that it was made of actual frog skin? I was setup! It was entrapment I tell you!

And secondly, I really need to see the schems. Without the schems, your descriptions of the functions are getting more and more beyond my feeble little mind's ability to understand.

It's like at the trial when the prosecution was trying to describe what actually constituted frog licking. I just wasn't sure whether I was guilty or not, until the Judge insisted that they draw some pictures. Then it all became clear to me.

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PostPosted: Sun Sep 17, 2006 9:09 pm    Post subject: Reply with quote  Mark this post and the followings unread

I'm not sure what the effects are of licking a frog skin bikini (closest I've come to that was a naughehyde thong), but the ill effects of one's wife catching one licking said bikini can be life-altering. Unless of course, she is the bikini-ee.

Schematics are nearing completion. In the meantime, there's this.

http://mypeoplepc.com/members/scottnoanh/sitebuildercontent/sitebuilderfiles/frogskin_bikini.mp3

Klee random realization of a bikini fabricated from the hide of a psychotropic amphibian (Bufo-Krunkuli)

Cheers,
Scott

Last edited by Scott Stites on Sat Nov 04, 2006 6:30 pm; edited 1 time in total
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PostPosted: Mon Sep 18, 2006 2:10 am    Post subject: Reply with quote  Mark this post and the followings unread

Right ... "frog skin bikini". Googled for images on that but nothing showed up. Probably meaning that with the right sort of marketing you quys could be rich. The tune for the advertisement is pretty OK already, just the right sort of jumpiness I'd say. And tasting like more.

Meanwhile I'm curious for the building plans as well Very Happy

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PostPosted: Mon Sep 18, 2006 3:23 am    Post subject: Reply with quote  Mark this post and the followings unread

Great soundtrack Scott!

Imagine a world-wide pre-release marketing blitz which is just pictures of scantily clad ladies, all wearing our frog skin bikini's, with Scott's soundtrack playing in the background and it ends with the words.
"Just lick it." Shocked Laughing

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PostPosted: Mon Sep 18, 2006 5:07 am    Post subject: Reply with quote  Mark this post and the followings unread

Uncle Krunkus wrote:

"Just lick it." Shocked Laughing

or maybe:
Posted Image, might have been reduced in size. Click Image to view fullscreen.
Very Happy
for more ideas click here
Shocked

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PostPosted: Mon Sep 18, 2006 7:34 am    Post subject: Reply with quote  Mark this post and the followings unread

Uncle Krunkus wrote:
And secondly, I really need to see the schems. Without the schems, your descriptions of the functions are getting more and more beyond my feeble little mind's ability to understand.


Me too I'm afraid. Although I've got the basic concept up there, the old grey matter is starting to suffer from engineer's droop Shocked

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PostPosted: Mon Sep 18, 2006 11:21 am    Post subject: Reply with quote  Mark this post and the followings unread

If you think of the normal sequencer as a Klee with only one bit active, that helps. Having more than one stage active at any given time is the whole gimmick of the Klee in a nutshell. Everything else follows that.

Here's a finished schematic for one section - it's exactly what I have on the breadboard for this particular section. It's really the heart of the Klee.

This section, which I couldn't resist calling "Clock and Load", handles the input clock and programming of the shift register.

We'll start at the clock input. Any Ken Stone afficiandos out there will recognize the input comparator - it's ripped straight off of Mr. Stone.

A signal applied at 'Clock In' will produce a high out of U1B when its voltage exceeds the reference voltage of approximately 2V, which is set by R25/R19. This means you can use any waveshape as the clock source - it can be a sine, triangle, sawtooth, pulse, whatever that will swing above 2V and back. As long as that voltage is above 2V, the voltage out of the comparator will be high. If the signal at clock in is below 2V, this signal will be low. This signal is inverted by one section of U2, converted to a negative going pulse by C9/R19, and the pulse is inverted again before it is applied to pin 1 of U3. This process produces a very narrow positive going pulse, which is used to generate the 'RClock' signal, which clocks the shift register ICs. With each RClock pulse, the shift registers shift their contents right.

When programming any sequencer, it's handy to be able to manually step through the sequence when tuning the various steps. Once you tune one step, you advance the sequence to the next step, tune that, and so forth. Same applies to the Klee, so SW19 is provided for that. Switch 19 is a pushbutton, momentary switch that, when held down, is debounced by U4. When the Manual Step switch is pressed down, it causes pin 3 of U4 to go high. As long as the switch is held down, this output will be high. This high is ORed through U3 with the high or low output of the clock in comparator to produce the signal 'Clock'. So, if the clock input is high, and/or the Manual Step switch is pushed, 'Clock' will be high.

'Clock' is used by the gate bus to form the output gates and triggers, but don't worry about that right now. On this board, it is used to illuminate the Clock LED, so one has a visual cue of how fast the input clock is ticking.

The output of U4 pin 3 is also inverted and processed by C10/R22 to form a negative going pulse signal. This negative going pulse signal is inverted again, and on pin 10 of U4, we have another very narrow clock pulse. This narrow clock pulse is ORed with the clock pulse from the clock input circuit. Again, this very narrow pulse used to generate the 'RClock' which is used to clock the shift registers.

So, either a positive voltage transition at the clock input and/or a push of the Manual Step switch will shift the contents of the shift registers right.

As long as the clock input is held high and/or the Manual Step switch is pushed, the 'Clock' signal will be high. Again, don't worry about the 'Clock' signal too much right now. That will come later.

OK, so I keep referring to the "contents of the shift register". First of all, the shift register is 16 bits long. A normal sequencer would have one bit high and the rest of the bits low in the shift register. The Klee can do that, but it can also make more than one bit high - you can have all 16 bits high if you'd like, which wouldn't get you anywhere, but you can.

The Model 2 Klee uses two CD4034s as its shift register. The Klee configures the CD4034s so that they each have 8 parallel inputs and 8 parallel outputs. That is the key to the programability of the Klee. Each of these parallel inputs (16 total because two CD4034s are used) can be either high or low. Lets say the shift register is empty:

0000000000000000

and you have all of the parallel lines low - *except* the first line, which you've set high:

1000000000000000

The output bits of the shift registers are all still low - you have to tell the shift register to load your one bit. So you hit 'load' and the output of the shift register is now:

1000000000000000

Now RClock clocks the shift register, and, behold, you now have:

0100000000000000

RClock clocks the shift register again, and now you have:

0010000000000000

And so on. On the 17'th count, that one bit would loop around back to position one. It's a normal sequencer.

Now, each of those bits has a pot associated with it. Lets say the first four bits have pots set for the following:

Bit 1 = 1V
Bit 2 = 2V
Bit 3 = .5V
Bit 4 = 3V

So your sequencer output is:

Step 1 1V
Step 2 2V
Step 3 .5V

Let's say, now, you've selected more bits to be loaded. Say bits 1 and 2. You set switches 1 and 2 'on' and hit the load switch. Voila - your shift register now has this pattern:

110000000000000

Now RClock clocks the shift registers and you have:

0110000000000000

Again RClock clocks the shift registers:

0011000000000000

And so on, with the bits looping around to the beginning once they run out of register.

But wait a minute - what's the voltage output now? The voltages of the active stages adds together! So now you have:

Step 1 = 3V
Step 2 = 2.5V
Step 3 = 3.5V

This is the "Klee" experience, and I enjoin you to bask in its Klee-ey goodness. Consider now instead of bits 1 and 2, you select bits 1 and 3 - now your first step is 6.5V, and everything after that will be different as well, without having adjusted a single pot. Obviously, you want to shoot for smaller increments in Klee sequences, but you get the picture.

So, back to the circuit. After that dissertation, you'll understand why all of those freaking switches are there (I'm referring to SW1 through SW16). These are the switches you use to program the shift register. When each switch is closed, it presents a low to the shift register at its bit position, and when it's open, it presents a high to the shift register at its bit position. Of course, the shift register ignores any changes on these switches until it is specifically told to load the values. That's why all that load circuitry is there.

The Load In input is supplied so that external signals can initiate a load of the bit pattern selected by the pattern switches. It works the same way as the clock in - a signal above 2V will produce a high out of the LM358 and a signal below 2V will produce a low. When the signal goes high, it is inverted, converted to a narrow negative going pulse by C7/R17 and then inverted to form a narrow positive going pulse, which goes to pin 1 of U3.

Manual Load SW18 is a momentary switch that is debounced and produces a narrow positive going pulse to pin 2 of U3 when it is pressed. U3 allows a pulse supplied by an input signal or a press of the Manual Load switch to be passed on to pin 8 of U3. Pin 9 of U3 accepts a signal that originates from the bus matrix, Bus 1 to be exact. When the Bus 1 Load switch, SW17, is closed, any stage that is directed to bus 1 will initiate a load when it goes high. Don't worry too much about that right now - it's function is as a sort of reset/reload. With 1 bit patterns, it allows one to have a count anywhere from 1 to 16, with more than one bit loaded, it truncates the pattern even differently, but the main point to remember is that this allows the pattern to reload itself before completely looping around.

So, a transition to high on the Load In Input, a push of the Manual Load switch, or a high selected from the gate bus will all produce a pulse at the output of U3, pin 10. A pulse at the output of U3 Pin 10 is what causes the shift register to load the pattern selected on the Pattern Switches. It uses U5 to do just that.

U5 is required to follow the shift register CD4034s strict protocol of when and when you cannot parallel load a pattern into it. This is what happens when pin 10 of U3 goes high:

The first section of U1 is clocked so that it produces a high at its Q output. This high at the Q output serves two purposes - it holds the parallel/serial load pin of each CD4034 high so that each CD4034 will now pay attention to what is on its parallel inputs, and it clocks the second half of CD4013. When the second half of the CD4013 is clocked, it produces a narrow pulse on its Q output. Again, this signal serves two purposes. The first task of this Q output is to briefly pull the Async pin of each CD4034 high - this allows the CD4034 to actually accept the parallel information supplied by the pattern switches. Immediately Q drops low, which sends it on the second half of its task. Once it drops low, C12/R20 and U2 convert this signal to a positive going pulse, which resets the first half of U5, which has been patiently holding the CD4034s parallel load skirt up while the second half of U5 can do its dirty deed. The first half of U5 then drops the skirt. Sorry about the analogy, but this stuff gets dry.

And that's it. So, to recap, this circuit allows one to:

1. Externally clock the Klee
2. Manually step the Klee
3. Program the Pattern Switches
4. Externally load the pattern
5. Manually load the pattern
6. Automatically load the pattern under control of the Gate Bus

There are some fancy things that can be added, which have been left out of the Model 2. Synchronous load (IE, the Klee waits for a clock pulse before it loads from external or Manual load), pause, skip, gated operation, etc are all nice things that can be added. But that's all for the more advanced Model 3. Stay tuned for the next installment of "As The Klee Turns"

Cheerio,
Scott

EDIT: Corrected schematic to replace doubled use of 'A' section of U3 (put in the proper 'B' section). This is version 1.01.

Edit2: Schematic has been revised since this post. Zip file with the latest revision is downstream in this thread. Check first post of thread to find exact whereabouts.


Klee_clock_and_load_101.JPG
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Klee Clock and Load Version 1.01 (minor schematic error on version 1.00 - the first section of U3 was depicted as being used twice)
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Last edited by Scott Stites on Sun Oct 08, 2006 5:04 pm; edited 2 times in total
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PostPosted: Mon Sep 18, 2006 1:14 pm    Post subject: Reply with quote  Mark this post and the followings unread

Scott Stites wrote:
Stay tuned for the next installment of "As The Klee Turns"


Will do !

thx fotr the long "intro" Very Happy

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PostPosted: Mon Sep 18, 2006 1:53 pm    Post subject: Reply with quote  Mark this post and the followings unread

All righty, then:

Episode 2: CD4034s Get Their Oats

If you recall, from episode 1, the Clock and Load circuit was labeled as the heart of the Klee. If that's the case, then the Stage Encoder circuit is surely its left ventricle.

Looking at the schematic, one can see now where the Switch n, RClock, PSA, and R Async signals go.

Each RClock pulse causes the contents of the registers to shift right.

When PSA goes high, the CD4034 now is aware its parallel input pins are even there.

While the CD4034 is looking at its parallel pins, R Async sneaks in, gives it a poke in the whiskers, and now the CD4034 outputs (the 'B' side) have the same bit configuration as its inputs (the 'A' side the 'Switch n' inputs are connected to).

PSA then goes low, and RClock is free to start shifting things right (or down, as it appears on the schematic).

The outputs of each CD4034 go to two different destinations. The 'Stage n' outputs (Stage 1, Stage 2, etc.) serve to activate CD4066 sections that feed a selectable voltage to the step pots themselves. Each output also goes to a section of a CD4050 buffer, which ensures that the signal has enough muscle to simultaneously drive an LED and go off to the gate bus to wreak its contrapuntal havoc (thanks Robert). The signals labeled 'Stp n' (Stp 1, Stp 2, etc.) are the signals that go to the gate bus.

The LEDs obviously are the LEDs one normally associates with any sequencer - they are lined up in a row of 16 LEDs so you can watch your sequence dance along - they indicate which stages are active. For example, if LED 3 and 11 are on, then the voltages on pots 3 and 11 are adding together to form the voltage output.

Getting back to the CD4034s, you'll notice that the last ouput of U1 (B8, pin 1) is fed to the serial input of the second CD4034 (pin 10 SDI). This provides the bridge so that bit 8 can 'walk across' and become bit 9 when the RClock pulse says 'shift right'.

This brings us to a vital function of the original Klee. Notice that the last output of CD4034 U2 doesn't simply loop back to the serial input of the first CD4034, U1. Instead, it goes to a switch that will allow this to happen if you want it to. The Pattern/Random switch SW1, when set to 'Pattern', will allow the 16 bit pattern you programmed in the last chapter to loop around forever and ever. However, when SW1 is in the 'Random' position, it allows something very different to happen.

I bet you guessed a random function, right? Yes. This is the portion of the circuit I nearly excluded because of my infatuation with looping patterns, which is certainly fun and predictable, if anything about Klee sequencing can be called predictable. But Uncle K's musing about stones inclined me to go ahead and put it on the breadboard, and I found I'd forgotten just how spiffy this function can be.

The Random function lets chance become the pattern programmer. Chance, as it turns out, has no restriction to how many bits the pattern is, or what order, or if it ever repeats in this lifetime.

Enter our faithful comparator, U3. There are two inputs to the comparator. One input is a variable voltage, set by the Reference Level pot. The other input is an externally applied signal, the level of which is controlled by the Random Input Level pot.

If the signal applied to pin 5 of U3, through the Random Input Level pot, exceeds the level set by the Reference Level pot, then the output of the comparator will be high. Otherwise, it will be low.

The signal applied to the random input connector can be any signal commonly found on a synthesizer - an LFO, a VCO, noise, sample and hold - anything that goes above ground in level.

The output of the comparator goes to two destinations. One is the 'Ref' LED, which lights whenever the comparator goes high. The other destination is the Random/Pattern switch.

If the Random/Pattern switch is set to 'Random' then the output of the comparator is funneled to the serial input of the first CD4034. When R Clock pulses to shift the register right, the instantaneous high or low value of the comparator is programmed as the first bit in the register. In other words, if the comparator happens to be high at the time, bit 1 is made high. If the comparator happens to be low at the time, bit 1 is made low. If it happens to be in between high or low, well, let the CMOS Gods sort it out. After all, it is a random function.

On the other end of the Shift Register, the last bit on U2, B8, jumps off the cliff and falls screaming into the void, never to be heard from again when RClock wields its deadly pulse.

So, using an external input, adjusting its level and adjusting the reference level can produce anything from intermittent bits, bursts of bits, or evenly distributed random bits. In a way, the reference control can be thought of as a 'probability of change' control. It could be modified to accept an external voltage to randomize it even further, though running the signal input through a VCA will do the same thing. The Ref LED is a good indicator that you're in the ball park. If it's not lit at all, your register becomes successively filled up with 0s with every pulse of RClock. If it's constantly on, the register fills up with 1's. If it's flickering, then things start to randomize pretty well. Note, it can appear to be on more than it's off, but one can still get a large amount of 0's. The LED is flickering faster than the eye can see. If it happens to flicker low for that .06 microseconds that the CD4034 will even consider it as a bit candidate, then bit 1 will be low.

The selected signal input makes just as much difference in the flavor of the random pattern sequence as the settings of the level control and reference pot. LFO's will be cyclical in their randomization. VCO's can be cyclical as well, depending on their relation to the clock frequency (a factor as yet unmentioned in the generation of random patterns). Noise generally produces the most evenly distributed random patterns. It was the noise generator of my DSC2000 that produced the frogskin bikini pattern.

Note that the load function is still active even in random mode. This can be taken advantage of to create half programmed/half random patterns through judicious selection of the reload switch on Bus 1, something to be explained in a later installment.

And thus ends chapter 2.

Edit: Schematic has been revised since this post. Zip file with the latest revision is downstream in this thread. Check first post of thread to find exact whereabouts.
Cheers,
Scott


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Last edited by Scott Stites on Sun Oct 08, 2006 5:05 pm; edited 1 time in total
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PostPosted: Mon Sep 18, 2006 3:19 pm    Post subject: Reply with quote  Mark this post and the followings unread

Damn, yet another cliff hanger .. can't wait to see that gate bus ...
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PostPosted: Mon Sep 18, 2006 3:44 pm    Post subject: Reply with quote  Mark this post and the followings unread

Gate Bus and Decoder are the only two chapters left, followed by the controls, gazzins, gazzouts listing.

Gate Bus is next, though logically the decoder should be. I'm still riding the fence on it, though - mainly, what ranges to make available. The nature of the Klee makes an available very low range of adjustment selection desirable - that way, it would be easy to tune up some microtonal sequences using more than the max of four pots I usually use for constructing Klee sequences. There are 16 pots available, might as well see what very low range of adjustment will do for it (I'm thinking a range that has 0.5V of adjustment for each pot - that's half an octave, easy for tuning small increments). Even the small increments add up in a Klee sequence - consider 16 pots with half steps on them. If all bits were high, that will still be 8 full steps above if they were all low.

But I'm getting ahead of myself here. This is my last design, BTW. I've found an opening in the bikini industry I just couldn't turn down.........

Cheerio,
Scott
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PostPosted: Tue Sep 19, 2006 2:55 am    Post subject: Reply with quote  Mark this post and the followings unread

I was going to say that I reckon the butler did it.
But now I'm not so sure. Smile

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PostPosted: Tue Sep 19, 2006 3:00 am    Post subject: Reply with quote  Mark this post and the followings unread

Like sands through the hourglass,
so are the clocks of the Klee.

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PostPosted: Tue Sep 19, 2006 11:25 am    Post subject: Reply with quote  Mark this post and the followings unread

Episode III: Gate Me? Gate You!!!! - The Gate/Trigger Bus

This one is a doozy - not a lot of circuitry there, and the function isn't that difficult to use, but it sure takes a lot in the way of explaining.......

The Klee sequence is a useful thing, but it really comes alive when one can distribute its control output in the same way its sequence is constructed. I've found that even a mundane sequence can come alive when the Klee distributes its events using a number of voices. In the Model 2 Klee, this distribution relies solely on providing a means to send out gate and trigger signals derived from the Klee sequence itself. The next, more advanced model will distribute actual Klee voltages as well (the sample and hold trick mentioned earlier in this thread).

The gate bus is nothing new to sequencers - the ARP 1601 had three gate busses, for example. The Model 2 Klee design also has three gate busses, and each bus actually will produce a trigger in addition to the gate signal (after all, ADSRs generally require both of these signals, and triggers are also useful for controlling other devices, such as drum voices). The difference in effect, again, is that a 'normal' sequencer only has one stage active at any time. Of course, this does not apply to the Klee, and therein lies its change of behavior.

I might mention that another addition is the 'Merge' function, also spoken of earlier in this thread. In short, the merge function will 'merge' two or more gates that are adjacent to each other on a bus into one unbroken gate. It will also produce one trigger for each 'merged' gate. For example, if Bus 1 has stages 1, 2 and 3 all switched to it, and one is using a standard 'one bit' sequence, instead of a separate, discrete gate for stage 1, stage 2, and stage 3, only one gate will appear and remain high for the amount of time it takes the sequencer to step through stages 1, 2 and 3. By the same token, instead of three triggers being produced, only one trigger will appear at stage 1 (stage 1 being the first stage in the adjacent row of three selected stages). Finally, if the merge function is switched off, all gates produced will be on as long as the clock input is high - the gate duration follows the clock duration. In the merged mode, if a gate is not merged with another adjacent gate, the gate duration will still last as long as that step is active - when the LED for that step lights up, the gate goes high, when the LED for that step goes off, the gate goes low.

Let's look at the schematic. The first item to call attention to is the Clock Delay sub-circuit, as everything is actually produced from it. The clock delay circuit produces a delayed version of the 'Clock' signal. 'Clock' is a signal produced on the Clock And Load board, which was discussed in chapter one of this explanation. This delayed version of the 'Clock' signal is called 'D_Clock'.

The reason why the clock has to be delayed will become apparent in a moment. For now, let's look at how the 'Clock' signal is delayed. The Clock signal is applied to U5, which sends an inverted copy of it through R36. C1 delays the rise time of this signal, by around 20 us or so. The second stage, again provided by U5, inverts this signal back to the original phase of the 'Clock' signal. Because U5 is a Schmitt trigger, the edges of D_Clock remain nice and crisp. So 'D_Clock' is a copy of 'Clock', but is offset in time by around 20 uS.

All gates and triggers produced on the Gate Bus are derived from D_Clock by ANDing stages with it. If a stage is active, in other words, if the bit corresponding to that stage is high, then that stage will produce a high when it is ANDed with D_Clock.

The heart of the gate bus is the switch/diode matrix in the center. Each switch is a SPDT On-Off-On switch. This means that these switches have a center position that disconnects either throw from the pole of the switch. The Stp n signals (Stp 1, Stp 2, etc.) originate from the Encoder circuit, which was covered in Episode 2. If you recall, a Stp signal goes high when the bit associated with that Stp is high. Each Stp n signal is assigned to its own bus switch through a diode.

Let's look at what happens when Stp 1 is high. If Switch 1, the bus switch STP 1 is dedicated to, is switched in the up position, it is switched to bus 1, and that high is fed onto bus 1. If Switch 1 is switched to the center position, the signal is not fed anywhere - more on that in a bit. If Switch 1 is switched to the down position, the high on Stp 1 is fed to bus 3.

For now, let's leave Switch 1 in the up position, switched to bus 1. This high signal is fed to pin 1 of U1, which is acting as a 16 input NOR gate - notice that all of the switches on Bus 1 can be fed through a diode to this section of U1. Its job is to go low if any Stp n signal switched to bus 1 goes high. So in our example, the output of this gate is forced low because Stp 1 is high and switched to bus 1. The next stage of U1 inverts this signal back to a high. So, the first two sections of U1 are actually acting as an OR gate. This high signal is sent to one input of a NAND gate, a section of U4.

This first NAND gate is acting as a sort of switch, really - its purpose is to enable or disable the Merge function. That's all it's doing.

The Clock signal, now delayed and re-named D_Clock, at this point is high, but then it is inverted by another section of U1. This inverted signal is sent to our Merge enabling NAND gate, specifically to pin 2 of U4. But we don't want to merge - not yet, nooo...not yet. We must see what happens down the road, then we'll get all fancy and start be-bopping and scattin' with the merge function.

So, because we want the merge function off, SW17 is left open. Because SW17 is left open, pin 1 of U4 is held high. So, pin 2 of U4 is low (our inverted D_Clock) and pin 1 of U4 is high (our signal that says 'don't merge') - this makes the output pin 3 high. Because Clock_D just transitioned high, this output pin has just transitioned high. When clock_D goes low, its inverted output will be high. Our Merge switch is open, so it's sending a high as well. Being a NAND gate, pin 3 then swings low. Do you see a trend here? If SW17 is left open, the output of this NAND gate follows the output of D_Clock. This is important to remember later on when we decide to merge.....

Meanwhile, the game is afoot -

Do you remember Stp 1, which is switched to Bus 1, and is high? What this whole example is about? Well, it's barrelling down the wire straight for our second NAND gate. This NAND gate, which doesn't mind at all that we just paid all the above attention to the Merge NAND gate, no really it doesn't, is what determines whether a gate and trigger is produced or not.

So, the high of Stp 1 crashes into pin 6 while the high out of our Merge NAND gate has a death grip on pin 5 and....the output of this NAND, pin 4, goes low. But wait a second....moments later D_Clock goes low, causing our Merge NAND gate to go low. While Stp 1 is still high, the Merge NAND gate output is low, so our Gate Length NAND output now goes high. So, as long as Merge is disabled, and the Gate NAND gate has a high on the bus feeding one input, its output will be the opposite of D_Clock. Take away the high on the bus, IE, no switch on bus 1 is feeding a high to the bus, then this output will remain high, regardless of what D_Clock is doing. It takes a high on the bus for this NAND gate to change output.

When our Gate dealing NAND transitions from high to low is when our gate and trigger signals spring to life. This high to low transition is processed by C2/R3 and a section of U1 to create a positive going pulse. The values of C2/R3 stretch the pulse width out to a around 1 ms wide. Hey - we have a trigger signal - problem is, it's a 0 to +15V trigger. Let's leave it at that and go back to the output of the NAND gate.

Now, remember, the output of the NAND gate has just transitioned low. This output is also inverted by another section of U1. The output at pin 8 of U1 is now high - and will stay high as long as Clock_D is high. This is our raw bus 1 gate signal. Like the trigger, it is sitting at a high of 15V. Not desirable for most synths.

So, now we have a gate and a trigger pulse at 15V levels. The gate is present at Pin 8 of U1 and the trigger is present at pin 10 of U1. Now we want to deliver these signals to the outside world, at +5V levels instead of +15V levels. In comes our handy LM358 comparator. Each section of the LM358 has a reference input fed by 2V, and both of our signals are well above that, so both sections of the LM358 are, at this point in time, putting out +15V. Then these signals encounter two resistors - R19/R27 for the gate comparator and R20/R28 for the trigger comparator. Each of these two resistor pairs cuts the output to 5V, but, even more, these resistor combinations provide the standard output impedance of 1K! This is a trick learned from Thomas Henry years ago.

The trigger, being a pulse, drops to 0V a millisecond or so after going high. The Gate stays at +5V as long as the D_Clock signal is high because of that whole thing mentioned earlier about the Gate Dealing NAND only allowing the Gate to be high as long as D_Clock is high. As soon as the D_Clock goes low, the gate goes low.

Now we have a gate and a trigger on the output of Bus 1, created by Stp 1 going high and being NANDed with a delayed version of the Clock signal. The output of the NAND is the gate signal, and a pulse derived from the rising edge of the Gate is our trigger signal. The signals are conditioned and sent from the Bus 1 Gate and Trigger outputs at +5V levels. But, a mystery remains: why is the clock delayed before it's ANDed with Stp 1?

Propagation delay. The CD4034 must be the slow moving lumber wagon of CMOS ICs. Oh, sure, your Klee will book along at audio rates, but on a macro-time scale, things seem to be a tad slower than with other, sleeker, sexier ICs.

This is what happens: The original Clock signal goes high - when it goes high, STP1 will not instanteously shift into place - there's a slight bit of propagation delay. When the clock goes low, then high again, it will shift the high in Stp 1 right. But, this does not happen immediately as mentioned before - there's a slight bit of propagation delay. So, when Clock goes high again, Stp 1 hasn't moved along just yet - so, for a brief instant, the tardy Stp 1 excites our gate dealing NAND gate all over again! This wouldn't be a problem if the next bit entering Stp 1 were a high - it wouldn't be noticed. But, if the next bit is a low, we still have just generated a trigger and the merest blip of a gate before Stp 1 moves on. Perhaps in some systems, the EGs wouldn't react to this very slim sliver of a high, but my EG's do - they have input comparators on them that can detect the most fleeting of voltages. I figure there must be some other numbnut in the world who put such sensitive comparators on the input of his EG, so I've chosen to defeat these little spikes.

The solution is to delay the Clock to give the shift register a chance to shift before it is ANDed with the clock. Because D_Clock waits enough time for the shift register to shift, the false signals never have a chance to propagate.

This leads us to the Merge function. Going back to the windy explanation above, we see that we left SW17 open, which allowed the output of pin 3 of U4 (our Merge NAND) to transition each time D_Clock transitioned. So, what if we close SW17? This leaves a low on that input of the Merge NAND gate. This means the output of this NAND gate will always be high - D_Clock has no effect on it now. We've just turned it into a yes man that says, "Whatever happens, my output is staying high".

This has a chilling effect on the output of U4, pin 4 - our Gate Dictactor NAND - it will now only transition high when Stp 1 goes low again, which means it will no longer use Clock_D as the arbiter of when a gate goes low, because the other input of this NAND gate, the one usually transitioning from low to high with each cycle of Clock_D, is now fixed high, thanks to our paralyzing of the Merge NAND. So when Stp 1 goes high, this output goes low and stays that way until Stp 1 goes high again.

Now it gets political. If the next step, Stp 2 is also switched to bus 1, when Stp 1 shifts right to Stp 2, the bus never goes low. So now the gate stays high even though Stp 1 is low, because there was no transition from low to high when the bit in Stp 1 shifted to Stp 2. Because the trigger is derived from the rising edge of the gate transition from low to high, no further trigger is generated.

So, the effect of the Merge function is:

1. If no adjacent step is switched to the bus, the gate lasts as long as the current step on bus 1 is high. This differs from the non-merged gate, which lasts only as long as D_Clock is high. A trigger is produced for this step.

2. If an adjacent higher step is switched to the bus, the gate on time extends to the duration of that step as well, and no further trigger is produced.

This explanation is valid if only one bit is programmed into the register. Lets imagine now that two bits are programmed into the register - say bits 1 and bits 4. If Stp 1 is switched to bus 1 and Stp 5 is switched to bus 1, only step 1 is applying its high to bus 1. Now the register shifts right. The high on Stp 1 is transferred to Stp 2, which, in this example is not switched to bus 1. However, the high on Stp 4 shifts to Stp 5, which *is* switched to bus 1. Bang! We've got no low transition on Bus 1, so the gate stays high and no further trigger is produced, even though Stp 1 and Stp 5 are not adjacent! Such is the mystery and madness of the Klee function. Predicting what will happen with anything becomes more complex - experimentation (IE, what happens if I switch this gate bus switch on with this pattern?) is the key to finding new angles on a programmed pattern.

Whew, that leaves one more note on Gate Bus 1 - that little "Gate Load" tag at the upper left of the switch/diode matrix. This simply means that whenever bus 1 goes high, it sends that high to the Bus 1 Load switch on the Clock and Load board. If that switch is closed, any high on Gate Bus 1 will initate a reload of the pattern programmed into the register with the pattern switches. If only one bit is active in the register, this functions simply as a reset control - say bit one is programmed for the first stage, and Stp 9 is switched to Bus 1. When the bit steps through to Stp 9, the pattern is instantly reloaded and the bit is reloaded into Stp 1. This results in an 8 step sequence rather than a 16 step sequence.

Once again the Klee function obfuscates things a bit - if the first bit is still left high, but bit 7 is programmed to be active as well, it turns into a two step pattern. Stp 1 and Stp 7 form the first voltage, Stp 2 and Stp 8 form the second voltage, then Stp 8 shifts to Stp 9, which throws the high on Bus 1, which loads the pattern back to Stp 1 and Stp 7.

Gate Bus 3 operates identically to Gate Bus 1, only Gate Bus 3 does not provide the optional signal for re-loading. So, all of the above applies if Stp 1 is assigned to Gate Bus 3 rather than Gate Bus 1.

Gate Bus 2 operates again in the same fashion, except for the fact that it acts upon the absence of a high on either gate bus 1 or gate bus 3. If there is no high on either of those two busses, then, through logic, it knows the switch is in the center position and it must deliver. D17 transfers the signal from gate bus 1 and D18 transfers the signal from gate bus two to Pin 1 of U3. This section of U3 is acting as a Mickey Mouse NOR gate, so if no high signal is present on either Bus 1 or Bus 3, then the output pin 4 goes high, and the same nasty, backstabbing process as the other two busses ensues.

Finally, we have the Master Gate and Trigger outputs. These outputs provide a gate and a trigger for each tick of the incoming clock pulse (delayed of course by D_Clock). The gates will always stay high as long as the input clock is high, and will go low when the input clock goes low.

So, after all of that, we have:

1. Three Busses to distribute gate and trigger signals to different destinations at different points in the sequence.

2. A master output that generates a constant stream of gates and triggers in time with the input clock.

3. A method to individually manipulate the gate times and number of triggers on each of the bus outputs.

4. A method to truncate the number of steps a particular sequence will have.

As far as enhancements to be seen in Model 3, there is the sample and hold function already mentioned. Picture, if you will, a narrower trigger produced along with the normal output trigger. This narrow trigger is used to sample the Klee voltage at that instant in time. Output that Klee voltage on a separate connector. Do that for all three busses. Now, not only can you distribute events throughout the Klee sequence, you can also overlap these events. Say on step 1, bus three triggers a long EG, and the sampled CV out is controlling a VCO that passes through a filter/VCA controlled by that EG. Step 2 is switched to bus 2 and fires a series of triggers to a different EG with a much shorter envelope - the Klee voltage is controlling that VCO that is passed through devices its EG is controlling. The effect is that the first VCO will hold it's note while the second VCO plays an ostinato underneath it. That's one mere example.

The other enhancement concerns the merge function. If Merge is off, the pulse width of the clock controls the gate duration, which is a cool feature. If Merge is on, the gate width is fixed for as long as a step is high, or if the steps run together, for as long as those combined steps are high. A third option, one derived from the ARP1601, is to generate internal blanking pulses. This would allow the gates to be fixed for the length of time a step is high, but would prevent them from merging. So, longer fixed gates would be generated, and a trigger for each gate would be generated, regardless of if the active steps were adjacent or not.

As it sits, the three gate busses provide a huge panopoly of functionality if one thinks of it any time at all. Up to four devices can be controlled uniquely from one sequence. Even a single voice will gain the ability of 'accenting' certain steps in the sequence. For example, gate its EG with the Master Gate out and retrigger the EG with selected trigger outputs from one of the busses.

Stay tuned for the Decoder Incident, coming to an electro-music near you......

Cheerio,
Scott

Edit: Noticed I'd accidentally deleted R22 and R30 - corrected and re-posted the schematic.

Edit 2: Schematic has been revised since this post. Zip file with the latest revision is downstream in this thread. Check first post of thread to find exact whereabouts.


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Last edited by Scott Stites on Sun Oct 08, 2006 5:07 pm; edited 3 times in total
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v-un-v
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PostPosted: Tue Sep 19, 2006 12:31 pm    Post subject: HOT HOT HOT!!!! Reply with quote  Mark this post and the followings unread

Scott, Unckle K, Jan and everyone else I've forgotten, this thread/ project is just too cool for words, so I've made it sticky- so it will never be lost in the EM vaults

(I intend to also make quite a lot of other stuff sticky too over the next few weeks Very Happy )

Tom

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PostPosted: Tue Sep 19, 2006 12:58 pm    Post subject: Reply with quote  Mark this post and the followings unread

Cool
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PostPosted: Tue Sep 19, 2006 2:55 pm    Post subject: Re: HOT HOT HOT!!!! Reply with quote  Mark this post and the followings unread

v-un-v wrote:
I intend to also make quite a lot of other stuff sticky too over the next few weeks

watch out for that sticky overdose Exclamation

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PostPosted: Tue Sep 19, 2006 3:34 pm    Post subject: Re: HOT HOT HOT!!!! Reply with quote  Mark this post and the followings unread

seraph wrote:
watch out for that sticky overdose Exclamation


Which reminds me, had my memory stick named sticky but renamed it after a customer asked if I did pot Very Happy

Anyway Tom is right, this is Cool Cool Cool , but I'm hoping Howard will make the list thing going. That one seems to be better for organizing stuff than stickiness.

Meanwhile I'm working on a stripped down version of the 16 pot Klee for the G2, so I'm not quite 100% ready for part III yet, but I'll catch up !!

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PostPosted: Tue Sep 19, 2006 4:10 pm    Post subject: Reply with quote  Mark this post and the followings unread

Quote:
Meanwhile I'm working on a stripped down version of the 16 pot Klee for the G2, so I'm not quite 100% ready for part III yet, but I'll catch up !!


That'll be interesting! I've usually restricted Klee sequences to four pots, but being able to change which four pots are used will be interesting - that's why I went with 16 on this one - also, it can still double as a 'normal' 16 step sequencer when one doesn't want to Klee. More pots used for a Klee sequence may be interesting as well, especially if tuned for low increments that add up - I'm thinking it might make for some interesting microtonal sequences.

Decoder is still in the works - I'm putting the finishing touches on it. Couldn't let it go without a slew of some sort or another. I've put in a David Brown design for that (no reason to re-invent) - linear and expo.

Voltage range selection for the pots is 0.5, 1, 2, 3, 4, 5, 6, 7, 8 and 9V - I figure 9 was close enough to 10, and I think that lower voltage range (0.5V) will be much more useful for multi-pot Klee.

Cheers,
Scott
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PostPosted: Tue Sep 19, 2006 4:30 pm    Post subject: Reply with quote  Mark this post and the followings unread

Scott Stites wrote:
I think that lower voltage range (0.5V) will be much more useful for multi-pot Klee.

It depends very much on the pulse density in the loop, for low densities the higher ranges might be usefull. Guess there will be a trade off when the number of pots gets large the steps will have to be very subtle, or the pulse density must be kept quite low. Anyway I thinks it's good it is selectable, and sofar 16 pots in my G2 patch does not seem too large a number.

BTW why don't you simply use a potmeter controlled attenuater after the step voltage summing ? Just because it would give more hassle tuning the thing ?

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PostPosted: Tue Sep 19, 2006 6:29 pm    Post subject: Reply with quote  Mark this post and the followings unread

I would have thought that it would be more versatile to start your voltage steps lower, say 1/12V and then go for "prime?" divisions plus their multiples, so: -
1/12V
1/8V
1/6V
1/4V
1/3V
1/2V
1V
2V
4V
8V
As the voltages get added together, this gives you heaps more possible increments in voltage and still a potentially large total. Maybe I'm missing something, or maybe the smell of the gum turpentine is taking it's toll! Laughing

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