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deleted_account-2192



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PostPosted: Wed Dec 05, 2007 7:47 pm    Post subject:  Deleted.
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blue hell
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PostPosted: Wed Dec 05, 2007 8:02 pm    Post subject: Reply with quote  Mark this post and the followings unread

Very Happy a miracle !

welcome

CMOS ports have a very high input impedance, they also amplify their input signals a lot. This means that when inputs are not connected to ground or Vcc through a low impedance path they will be very sensitive receivers and may result in an output signal.

I may not have read you correctly, but from your description I think you might have something like that.

Apart from that the gates are pretty fast, certainly capable of following AM radio signals. When there is any non linearity present in the gate I think that should be enough to do crude AM detection.

Don't you /dare/ to change a thing in that circuit Exclamation Laughing

(you should make a recording with it)

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also .. could someone please turn down the thermostat a bit.
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deleted_account-2192



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PostPosted: Wed Dec 05, 2007 8:04 pm    Post subject: Reply with quote  Mark this post and the followings unread

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deleted_account-2192



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PostPosted: Wed Dec 05, 2007 8:55 pm    Post subject: Reply with quote  Mark this post and the followings unread

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françois



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PostPosted: Thu Dec 06, 2007 2:50 am    Post subject: Reply with quote  Mark this post and the followings unread

Strange, admittedly. I guess you are using CMOS NAND gates, which can easily "afford" 15V power supply. (6V is clearly too high for TTL gates).
Now, if one (or more) inputs of a gate is left open, it behaves like a high-impedance antenna, and the Schmitt trigger inside does make crude AM detection.
But if _all_ gate inputs are properly connected, there should be no interference at all. Or you are running them at too high a frequency (remember, CMOS is relatively slow). But if you stay in audio ranges, this should not happen.
Or your chip is defective? CMOS are quite fragile, and careless soldering may have damaged the chip... Dunno.

-- françois
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bugbrand



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PostPosted: Thu Dec 06, 2007 3:23 am    Post subject: Reply with quote  Mark this post and the followings unread

Power supply de-coupling perhaps?

It is standard to have an electrolytic cap over the power supply to stabilise the power -- and I don't see that on the schem.!. Try adding a 100uF cap from V+ (6v in your case) to Gnd where the power comes in (oh, observe polarity - electrolytics must be the right way round - positive to positive, negative to ground)

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Uncle Krunkus
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PostPosted: Thu Dec 06, 2007 5:25 am    Post subject: Reply with quote  Mark this post and the followings unread

You do have all the unused inputs connected to ground don't you?
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deleted_account-2192



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PostPosted: Thu Dec 06, 2007 5:27 am    Post subject: Reply with quote  Mark this post and the followings unread

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Tim Servo



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PostPosted: Thu Dec 06, 2007 12:15 pm    Post subject: Crazy stuff.
Subject description: CMOS
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ayeyen wrote:
Uncle Krunkus wrote:
You do have all the unused inputs connected to ground don't you?


I don't. I didn't know I had to. I'll try both of your suggestions. Thanks! Smile


Uncle K speaks the truth. One of the cardinal rules in playing with CMOS is that ALL inputs must be connected to either V+ or GND. Leaving a CMOS input "floating" may cause it to oscillate between 1 and 0, and could very well be the source of your problem. Floating inputs can also cause the chip to consume more power than it normally would. One common trick is to use a resistor (10K or larger) connected to V+ or GND to pull the input high or low (these are called pull up or pull down resistors, for obvious reasons). Using a pull down R lets you keep an input at 0 until you apply a positive voltage (like with a normally open switch, for example).

Good luck with the NANDSYNTH, looks like a fun project.

Tim (also oscillates when left floating) Servo
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deleted_account-2192



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PostPosted: Thu Dec 06, 2007 2:35 pm    Post subject: Reply with quote  Mark this post and the followings unread

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EdisonRex
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PostPosted: Thu Dec 06, 2007 3:24 pm    Post subject: Re: Crazy stuff.
Subject description: CMOS
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ayeyen wrote:
So, say I'm only using the first oscillator. I would connect all the other inputs to ground using 100k resistors?


Or V+. depends on what you want your timings to look like. If you are running N logic, go high, if I remember the rules, because in N logic, high is false, and it was because of noisy environments you did this.

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deleted_account-2192



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PostPosted: Thu Dec 06, 2007 3:31 pm    Post subject: Reply with quote  Mark this post and the followings unread

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PostPosted: Thu Dec 06, 2007 3:36 pm    Post subject: Reply with quote  Mark this post and the followings unread

ayeyen wrote:
I'm not entirely sure what that means...


NAND = negative AND. we're dealing with logic that runs negative, meaning it's the opposite of positive logic. You need to look at logic tables.

negative logic is, well, negative, not necessarily opposite, to positive logic.

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deleted_account-2192



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PostPosted: Thu Dec 06, 2007 4:01 pm    Post subject: Reply with quote  Mark this post and the followings unread

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PostPosted: Thu Dec 06, 2007 4:30 pm    Post subject: Reply with quote  Mark this post and the followings unread

ayeyen wrote:
I know that. I just wasn't sure of why you would go high on N logic. Because high becomes low?


Well that's the point of negative logic. Your low states aren't as susceptible to noise and crap. because your low states are high instead.

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PostPosted: Thu Dec 06, 2007 7:33 pm    Post subject: Reply with quote  Mark this post and the followings unread

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PostPosted: Thu Dec 06, 2007 7:38 pm    Post subject: Reply with quote  Mark this post and the followings unread

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PostPosted: Thu Dec 06, 2007 7:51 pm    Post subject: Reply with quote  Mark this post and the followings unread

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PostPosted: Thu Dec 06, 2007 8:56 pm    Post subject: Reply with quote  Mark this post and the followings unread

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goodrevdoc



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PostPosted: Thu Dec 06, 2007 10:27 pm    Post subject: Reply with quote  Mark this post and the followings unread

the resistors tying the unused inputs to ground don't have to be all the same value, or any specific value for that matter. Is this the schematic you're using:
NANDSynth
If so, then there are no unused inputs and it would appear that the pots are supposed to interfere with one another.
-justin
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Randaleem



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PostPosted: Fri Dec 07, 2007 3:09 am    Post subject: Reply with quote  Mark this post and the followings unread

ayeyen wrote:
Wow, nothing works.

Hi ayeyen (Ian?). First, Welcome to electro-music!

You didn't say which NANDsynth site you were drawing from, but of all I've visited since you began posting, this one seems to have the most clear and complete information: http://misusage.org/wordpress/?p=23

FWIW, it comes up first in a Yahoo search on "nandsynth".

Quote:
I put a 100uF capacitor between + and - coming out of the battery pack before the circuit, and it changed the pitch and such of the oscillation! So I removed it.

Please consider that it might have changed it for the better. I'd put it back in, myself. near where the battery power enters the circuit board. Perhaps using a smaller one, say 10 to 47uF. (Not that the bigger size is a problem in this case!) Just that 100uf is probably bigger than you NEED. It won't hurt anything to use it, until you have a bunch of boards with 100uf "Filter" caps fed from one power supply. Then inrush current to charge all the big caps at power up can be a problem, causing the fuse of your power supply to blow, or your batteries to get hot.

Another thing you need is some smaller caps, say .1 or .01uF, at both the power supply entrance to the board AND as near to the CMOS chip as you can get it. With multiple CMOS chips, you will want multiple caps, one for each chip if possible. Sometimes on a densely populated circuit these caps are only used every few IC's. But more is better.

Without these small caps to bypass the high frequency noise of the CMOS switching to ground, you WILL have problems. Of exactly the type you're describing. CMOS switches (gates) switch very quickly, and this creates high frequency spikes, which will create havoc in the circuit unless they are held under control with local "bypass" capacitors.

The larger 10-100uF "filter" caps across the main supply do nothing to mitigate noise at higher frequencies. They are more like the "pond" that the local smaller capacitor "firefighters" draw from to put out the "fires" from the "lightning strikes" caused by the fast CMOS switching.

Quote:
Trying the pull-up resistors in a second.

Quote:
I haven't got enough resistors above 100k.

I'm not sure if this was clearly stated, but you don't need ANY resistors for tieing UNused CMOS inputs to Hi OR Lo. And you can tie them either way with no change in the result. OTOH, TTL logic needs to be tied high or it wastes current. But with CMOS it makes no difference. Tie any and all unused inputs directly to whichever power supply line is closest, hi or lo. Pullup Resistors are used with open collector outputs, to allow combining them as so-called "wired-ORs", and to allow for driving the pin LO to get both hi and lo states. .

Quote:
What can I do now? Just tie them to ground with wires? Or to +? Lemme try some things.

Have a look at the link I've listed. It shows a well thought out approach to the circuit I believe you're building. and has some good links too. EDIT: However, it doesn't have or detail the kind of typical capacitor filtering that is suggested here and in previous replies. IMO, it is almost always a good idea to include these in your own versions of online circuits to get the best results quickly!

On that note, it's probably always a good idea to post the specific circuit or URL of circuits you ask about here at e-m. There are SO many variations of circuits that might share a common name, that without this vital information you'll get a scattershot of answers as each person tries to answer based on possibly erroneous assumptions about what you're actually doing.

Finally, you may not realise that a solderless breadboard and CMOS chips are not always a reliable combination when prototyping. (Notice that the link I provided is using a stripboard prototyping board, rather than the common "whiteboard" solderless type. The problem is that the solderless whiteboards have a LOT of stray capacitiance, and with CMOS being as sensitive as it is, you will need even more bypass caps and perhaps "extra" measures to test CMOS circuits this way. Such extra measures may include more caps, multiple chips (when the final design will use only one) added r/c filters on I/O, slower clocking, etc.

Good luck, and Kind regards, Randal

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PostPosted: Fri Dec 07, 2007 3:24 am    Post subject: Re: Crazy stuff.
Subject description: CMOS
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ayeyen wrote:
So, say I'm only using the first oscillator. I would connect all the other inputs to ground using 100k resistors?


Hi ayeyen,

Not necessarily. Tim was telling you how pullup or pulldowns are sometimes used when inputs are active in circuits. UNused inputs may be tied directly to hi or lo.

Kind regards, Randal
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deleted_account-2192



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PostPosted: Fri Dec 07, 2007 5:16 am    Post subject: Reply with quote  Mark this post and the followings unread

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PostPosted: Fri Dec 07, 2007 5:48 am    Post subject: Reply with quote  Mark this post and the followings unread

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blue hell
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PostPosted: Fri Dec 07, 2007 5:56 am    Post subject: Reply with quote  Mark this post and the followings unread

ayeyen wrote:
Unless you cheated and googled me. Very Happy


Laughing Randal is quite some Googler indeed, you figured that out pretty quickly Very Happy

Sorry when my first response was a bit cryptic, but it seems that meanwhile enough words have been used by others to explain what I meant. Just be sure to have all inputs connected to something, even when you do not use that port.

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also .. could someone please turn down the thermostat a bit.
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