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JovianPyx

Joined: Nov 20, 2007 Posts: 1079 Location: West Red Spot, Jupiter
Audio files: 123
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JovianPyx

Joined: Nov 20, 2007 Posts: 1079 Location: West Red Spot, Jupiter
Audio files: 123
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Cynosure

Joined: Dec 11, 2010 Posts: 482 Location: Toronto, Ontario - Canada
Audio files: 29
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Posted: Sun Nov 11, 2012 5:45 pm Post subject:
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It sounds awesome. Amazing job! _________________ jacobwatters.com |
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JovianPyx

Joined: Nov 20, 2007 Posts: 1079 Location: West Red Spot, Jupiter
Audio files: 123
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Posted: Tue Nov 20, 2012 3:14 pm Post subject:
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I have two more samples. They are both from a MIDI file I adapted for the Harpie.
One has the reflection filter Fc low, the other has the setting higher.
The piece is "Entry of the Gladiators" by Julius Fucick. Many of you will recognize it. I was playing different MIDI files through the Harpie and twizzling the timbre knobs and I like the way it plays this. If you listen, I hope you like these.
| Description: |
Lower reflection filter setting Entry of the Gladiators by Julius Fucick |
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Fucick_Entry_of_the_Gladiators_lower_filter.mp3 |
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2.74 MB |
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51 Time(s) |
| Description: |
Higher reflection filter setting Entry of the Gladiators by Julius Fucick |
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| Filename: |
Fucick_Entry_of_the_Gladiators_higher_filter.mp3 |
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2.76 MB |
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57 Time(s) |
_________________ FPGA Synth Stuff
FatMan Mods
dsPIC Synth Stuff I am formerly known as ScottG here Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat?
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elmegil

Joined: Mar 20, 2012 Posts: 983 Location: Chicago
Audio files: 14
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Posted: Tue Nov 20, 2012 7:52 pm Post subject:
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Got any Scott Joplin files?
That sounds awesome. I know, I need to find a new adjective. |
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JovianPyx

Joined: Nov 20, 2007 Posts: 1079 Location: West Red Spot, Jupiter
Audio files: 123
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Posted: Fri Nov 23, 2012 9:15 am Post subject:
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I would like to thank Tom Wiltshire (who may be a member here) and Blue Hell for their help in getting things started up with dsPIC development. _________________ FPGA Synth Stuff
FatMan Mods
dsPIC Synth Stuff I am formerly known as ScottG here Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat?
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elmegil

Joined: Mar 20, 2012 Posts: 983 Location: Chicago
Audio files: 14
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Posted: Fri Nov 23, 2012 9:20 am Post subject:
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And thank you for documenting your steps, so there's a chance some of us might follow (eventually...backlog.... ) |
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Blue Hell
Site Admin

Joined: Apr 03, 2004 Posts: 19580 Location: The Netherlands, Enschede
Audio files: 116
G2 patch files: 317
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Posted: Fri Nov 23, 2012 12:30 pm Post subject:
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Glad I could help Scott, you're doing great stuff with it! _________________ Jan |
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JovianPyx

Joined: Nov 20, 2007 Posts: 1079 Location: West Red Spot, Jupiter
Audio files: 123
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Posted: Mon Nov 26, 2012 4:41 pm Post subject:
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I've built another DIY stripboard dsPIC with a Microchip 23K256 SPI SRAM. This is a 32 kilobyte SRAM organized in bytes. I connected the SRAM to the dsPIC with 2.5 inch wires and used no termination. The SPI SRAM operates nicely at an SPI data rate of 10 megabits per second (max for the dsPIC).
One thing I discovered is that the SRAM bar-CS pin cannot be tied low to force the IC to always be selected. The documentation could be a bit more clear about the actual function of bar-CS. They call it "chip select" which indeed it is, but it also serves to terminate the previous command. If bar-CS is simply help low, the SRAM does not function correctly. Each full transaction to or from the SRAM requires:
1) Bring bar-CS low
2) Send command
3) If write, send data. If read, accept the read data
4) Bring bar-CS high
In the documentation it is mentioned that bringing bar-CS high terminates the previously executed command. It does not clearly state that each SRAM transaction must be bracketed by a bar-CS low and bar-CS high. When bar-CS is low, it selects the SRAM and causes it to enter command mode. When bar-CS is raised, the SRAM terminates whatever it was doing (which is fine if it is timed so that the previous transaction is fully completed).
EDIT ADD:
In order for read from SRAM operations to be successful, it is necessary to make sure that the data being read from the SRAM SDO pin remains synchronized at all times. The dsPIC will shift data on SDI in whether it is a read operation or not. It is up to the driver to figure out how to do this. In my simple test program, I just wrote code to read the buffer register for each byte written to SDO. Most of these are dummy reads, but they keep the register synchronized so that when the real read data is there, it can be read out of the register. This is a bit confusing because one might think that if they are in the process of sending command data to the SRAM, then there's no valid data to read - and that is true, but if the dummy reads are not done, the SPI overrun indicator bit is set and further attempts to read the SDO line will fail. I am now looking into using DMA so that perhaps I can avoid using up CPU cycles to manage these reads. If the reads can done by the DMA controller, then this is work that gets done "for free" so to speak. (I do hope this last paragraph makes sense, it's late and I'm very tired, but wanted to add this information). _________________ FPGA Synth Stuff
FatMan Mods
dsPIC Synth Stuff I am formerly known as ScottG here Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat?
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JovianPyx

Joined: Nov 20, 2007 Posts: 1079 Location: West Red Spot, Jupiter
Audio files: 123
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