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Temp compensation resistor for VCO expo converter
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m.o



Joined: Jul 05, 2014
Posts: 27
Location: Sweden

PostPosted: Sat Jul 12, 2014 5:41 pm    Post subject: Temp compensation resistor for VCO expo converter Reply with quote  Mark this post and the followings unread

Edit: Sorry I realize now that these are not the same - I'll go back in my corner now
Sad

Hi guys,
Ahem, I thought I had this tempco business figured out but reality once again has slapped me down to earth Smile

So I'm working on a VCO design, pretty much standard thing with two transistors for expo conversion, op-amp integrator going into an op-amp comparator that empties the integrator cap with a transistor.

For expo conversion I'm using BCM847BS which is a pair of matched transistors in one package.

Not my problems come with the tempco resistor before the expo transistors.
As I understand it I need to compensate the voltage going into the base of the expo by +3300ppm/C (0,33% increase per degree C temp).

My implementation right now is that I have the CV input buffered to unity by an op-amp, then I have a voltage divider;
At the "top" I have a 10kOhm NTC with -3430ppm/C (close enough I hope), then a 100 Ohm trimpot with the wiper going to the base of the expo tranny, and under that a 100 ohm resistor to ground.

* The NTC is a SMD mounted on a small adapter sub-board together with (besides) the transistor package, I'm planning to put a gob of epoxy covering the NTC + transistors, but I haven't yet.

I was under the impression that this would be pretty much equal to what René Schmitz shows in figure 5 in his "Whats that exp and tempco stuff? " -page (http://www.schmitzbits.de/expo_tutorial/index.html).

However when I try it, my oscillator drifts a lot (from an initial 300Hz it drops to ~120Hz over about 30-50 minutes), and If I open my window it starts climbing.

What am I doing wrong here?

Did I get it all backwards?
I tried simulating the voltage divider as well as my whole VCO in LTSpice and it looks decent there, could be doing it wrong though?

Attached picture is my way of simulating the temp dependent resistor...


tempco sim.jpg
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tempco sim.jpg


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Janvier



Joined: Aug 12, 2014
Posts: 13
Location: Montréal

PostPosted: Tue Aug 12, 2014 4:46 pm    Post subject: Reply with quote  Mark this post and the followings unread

I think this is because you are using a NTC resistor. This setup, explain by René is for a PTC resistor. But you can look at the bottom of page there is the setup for a NTC resistor.

Also, maybe your Iref for the log converter is too big. What's your Iref ?
And finally the rBE of your transistor should be small enough.

The LM394 was a great supermatched pair NPN, but unfortunately they are discontinued. DAMN!!
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m.o



Joined: Jul 05, 2014
Posts: 27
Location: Sweden

PostPosted: Tue Aug 12, 2014 5:27 pm    Post subject: Reply with quote  Mark this post and the followings unread

Janvier wrote:
I think this is because you are using a NTC resistor. This setup, explain by René is for a PTC resistor. But you can look at the bottom of page there is the setup for a NTC resistor.

Also, maybe your Iref for the log converter is too big. What's your Iref ?
And finally the rBE of your transistor should be small enough.

The LM394 was a great supermatched pair NPN, but unfortunately they are discontinued. DAMN!!


Thanks for your reply.

Well, what I realized after posting that first post:
A circuit with a small PTC at the bottom of a voltage divider like that, the difference in resistance of the whole divider due to temp is really small, while you still get the "trimming effect".

In my circuit with a large NTC on top, resistance change will affect the total resistance of the whole divider much more which will affect the relationship much more.

(I think)

That last picture on the bottom of Renées page seems clever now that I look again, but I'd like a little more explanations around it.

What I did for now was to simply increase the values of all the resistors in my divider by a factor 10 - I'm not saying it's totally right, but I got rid of that dramatic drift I had before.

I also have some PTCs I'm considering giving up and just going that route if the drift becomes a problem again, but they were a bit more expensive than the NTCs.

I use BCM847BS in my expo converter, it's a factory matched (not super-matched I guess) pair in a 6-pin capsule, seems to work fine so far.
rBE is not mentioned as such in the data sheet unfortunately.

I have actually been over the Iref recently, when I wrote the OP i was at roughly 120 uA, which probably was a bit much for what I needed - I'm now aiming for about 25uA.
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Janvier



Joined: Aug 12, 2014
Posts: 13
Location: Montréal

PostPosted: Tue Aug 12, 2014 6:32 pm    Post subject: Reply with quote  Mark this post and the followings unread

For the Iref, for easier calculation. You an even use a 10uA current. So if your supply is 12V, you put a 1.2M. If your supply is 15V then a 1.5M.

I can't explain to you everything. Im in the same process as you. Im trying to understand the expo converter too. So I don,t understand everything yet.

But I think that the simplest way to see the thing is that the voltage at the base of the transistor when temperature compensated should be near 17.3mV. Which mean that if you feed into the CV input 1V, the output of the summing stage should be 17.3mV. This is what I understand. So you need to set the summing stage to get near that value. Then using a trim to adjust properly.

To make it short. If my previous point is right. You need only two things:
1. Knowing how to setup a tempco expo converter (transistor NPN or PNP pair and its Iref)
2. Set your summing stage in a way that if you feed into its input 1V then your output should be around 17.3mV

I don't have right now some calculation I made on different schematic to see if this was true. But I tried on one Rene's schematic and on the VCO-555 schematic of Thomas Henry. Both converters have a different configuration. But calculating the resistor values considering a 1V on the 1V/Oct input. The result are near that 17.3mV. I will put it on paper and post it.
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m.o



Joined: Jul 05, 2014
Posts: 27
Location: Sweden

PostPosted: Wed Aug 27, 2014 4:03 pm    Post subject: Reply with quote  Mark this post and the followings unread

Update again.

So I spent yesterday evening doing Spice simulations.
I discovered that I had wrongly assumed the default (in Spice) temp was 25C while it actually is 27C... Rolling Eyes

The two voltage dividers in the first post are indeed different, I also did some algebra to confirm, but you can get them pretty close (according to spice).
I could get the difference between the two dividers down to a millivolt (DC sweep, temp stepping 25 - 35 - 45 -55).
I again changed one of my VCOs to 10kNTC - 100 Ohm pot - 100 Ohm - ground, and it did not show the same drastic drift as I describe in my first post...
It responded worse to ambient temperature changes than a "classic" PTC-in-in-the-bottom VCO but it wasn't that bad, drifted from 214Hz (stabilized for a while) up to 224Hz when I opened the window.
One factor is that my NTC is actually -3430ppm/K rather than the 3300 that I understand it's supposed to be for best results (the PTC in my other VCO has this value).

I don't know how to explain what happened earlier; I have made other improvements to the VCOs since the last test (getting more correct reference current, changed to a FET reset circuit) or maybe I did something else wrong (like wrong value components or something).

Last edited by m.o on Fri Aug 29, 2014 2:56 pm; edited 1 time in total
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Janvier



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PostPosted: Thu Aug 28, 2014 5:38 pm    Post subject: Reply with quote  Mark this post and the followings unread

Do you have a normal resistor in parallel with you NTC ?
And what is the OPAMP you are using in your summing stage ?
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m.o



Joined: Jul 05, 2014
Posts: 27
Location: Sweden

PostPosted: Fri Aug 29, 2014 10:09 am    Post subject: Reply with quote  Mark this post and the followings unread

Quote:
Do you have a normal resistor in parallel with you NTC ?

No.

Quote:
And what is the OPAMP you are using in your summing stage ?

TL074
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Janvier



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PostPosted: Fri Aug 29, 2014 4:50 pm    Post subject: Reply with quote  Mark this post and the followings unread

Can I see your schematic from the summing stage to the tempco... Im trying to help but without seeing a schematic is a bit hard to give good answer lol
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m.o



Joined: Jul 05, 2014
Posts: 27
Location: Sweden

PostPosted: Fri Sep 05, 2014 12:20 pm    Post subject: Reply with quote  Mark this post and the followings unread

* I posted my schematic in the other thread here.

I found some articles indicating the use of a regular resistor in parallel with an NTC is done to somewhat straighten out the non-linearity of some (most?) NTCs.

My Spice models have all had the tempco modeled as totally linear...


On that note, I made an overly elaborate spice schematic for using an NTC in a op-amp negative feedback path here Shocked

The second one show how you can possibly use this to compensate a tempco with the wrong coefficient by placing another resistor in series with it (and increasing the input resistor to the op-amp equally).

(these are still assuming totally linear NTCs)

The schematics has a typical saw-tooth capacitor-integrator to easily plot and seen the results.


NPN current sink tempco.pdf
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NPN current sink odd tempco value.pdf
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