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 Forum index » DIY Hardware and Software » Microcontrollers and Programmable Logic
Avnet Spartan-3A Dev Board Synth
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JovianPyx



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PostPosted: Mon Oct 27, 2008 7:06 am    Post subject: Avnet Spartan-3A Dev Board Synth Reply with quote  Mark this post and the followings unread

Subject says it, with the help of Eric Brombaugh's DAC board (Cirrus CS4344, stereo, up to 200 KHz) and a home brew MIDI connector, I've been able to port my PolyDaWG/8 design to the board where it works quite well. Sample rate is 200 KHz.

PolyDaWG/8 is an 8 voice polyphonic MIDI synthesizer implementing tight string models using the Karplus-Strong method. This is the same synth I designed for the Spartan-3E Starter Kit board (with 12 bit DAC).

EDIT ADDED: I've placed information and source code at:

http://home1.gte.net/res0658s/FPGA_synth/

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okvern



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PostPosted: Wed Oct 29, 2008 9:24 am    Post subject: Reply with quote  Mark this post and the followings unread

Hi ScottG,

This is very interesting! Could you provide a link for the DAC board schematic and/or layout? There doesn't seem to be one in the documentation--searching led me to Eric Brombaugh's site, but I had no luck finding it there. Forgive me if I've missed something obvious.

Thanks,

Ole
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JovianPyx



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PostPosted: Wed Oct 29, 2008 9:48 am    Post subject: Reply with quote  Mark this post and the followings unread

Ok, here's what I know...

A while back, on the Synth-DIY list, Eric mentioned these boards as a little group distribution project. Several/many were interested. He got the boards etched professionall and built up a few prototypes. He provided a nice "driver" for it and then sent one to me for eval and testing. I was quite satisfied with it.

Eric recently told me that he has decided to go forward and offer these for sale, at least on a one time basis (no prediction as to when). I just searched and I cannot seem to find his site, but I had been there months ago. I know he had images of the boards in various stages of build, but I don't remember seeing a schematic. I would bet, however, that he did what I would do - start with the example schematic in the datasheet since the DAC is considered an audio device, my guess is that the circuit will work in most/all cases. Whatever he did, it's working for me. Cool There's really not much to hooking the DAC up, some clock lines and data come from the FPGA into the DAC, outputs are pretty simple audio stuff.

One nice thing about this is that there are lots of dev boards made by Digilent that have the 6 pin "Digilent port" into which this plugs. I have 3 different boards that all support at least 2 of these connectors.

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JovianPyx



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PostPosted: Wed Oct 29, 2008 10:50 am    Post subject: Reply with quote  Mark this post and the followings unread

More Info:

I finally found Eric's page (Google can be irritating) on this.

http://members.cox.net/ebrombaugh1/synth/audiodac/index.html

Near the bottom of the page is a link for the schematic, it comes in PDF format. As I noted in my last post, this is a rather generic thing.

The "driver" code I mentioned is also available at the above link. This driver code is the basis for what I use to interface to my projects. It was functional as is and needed only minor tweaking to allow using the full range of clocks and sample rates allowed. One of the wonderful things about HDL is that it's pretty easy to port code from one FPGA to another. I found it rather easy to move the code to a Spartan-3A DSP 1800 - in fact, the code itself was used as is, I needed only configure an appropriate clock for it.

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okvern



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PostPosted: Wed Oct 29, 2008 11:06 am    Post subject: Reply with quote  Mark this post and the followings unread

Hi ScottG,

That's perfect, thanks!

Ole
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JovianPyx



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Posts: 1214
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PostPosted: Fri Dec 02, 2011 7:49 am    Post subject: Reply with quote  Mark this post and the followings unread

I've been able to add echo/delay to this synth using two 23K256 ICs from Microchip. Maximum echo/delay duration is .65536 seconds.

I'd done this with the FM Bell synth too and learned some things there that I've had to apply to this one as well.

One thing is that, especially in a crowded design, it's apparently important to tell ISE to try to put the final flip-flop that drives an FPGA pin into the IOB instead of a fabric flip-flop and routing to the pad. The extra time it takes for that routing causes garbage to appear in the echoes due to data errors.

My first design attempt (at using the SPI SRAMs) used two parallel SPI busses to decrease access time, but this proved to be unworkable in that ISE wasn't able to put all of the end of line flip-flops into the IOBs. When I changed the design to a single shared SPI bus, the timing constraint violations abated and it started to work correctly. Converting to a shared SPI bus removed the need for 3 FPGA pins which made it easier for ISE to use the IOB flip-flops.

In the case of PolyDaWG, additional rework was required. The design had been working at a sample rate of 200 kHz which did not allow enough time for the SRAM to complete a read word and a write word operation. The solution I used was to drop the sample rate to 50 kHz and run the synth 4 sample cycles for each DAC cycle effectively decimating from 200 kHz to 50 kHz. This allowed the use of the SRAM for the delay effect without any undesirable audio problems.

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Last edited by JovianPyx on Mon Dec 05, 2011 7:50 am; edited 1 time in total
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Dougster



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PostPosted: Mon Dec 05, 2011 6:53 am    Post subject: Reply with quote  Mark this post and the followings unread

Looks like Eric's page has moved...

http://ebrombaugh.studionebula.com/synth/index.html

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