Xilinx's MIG (Memory Interface Generator)

JovianPyx · Posted: Fri Jan 13, 2012 9:47 am Post subject:

While working on MIG again, I note some things that went over my head before.

And also - the feedback path on the Spartan-3E Starter Kit board is indeed present. This was proven by a friend who designed a test that causes the rightmost LED to flash if the trace is there and connected. It shows up in the schematic and the LED on all 4 of my boards flashes indicating that it is present.

The MIG will generate an interface either with or without a DCM. When allowed to add the DCM, all it will do is generate 2 clock phases, clk0 and clk90 for the interface. Even though you tell the MIG what the clock should be - it does not modify the frequency of the incoming clock. That must be done external to the DDR SDRAM interface.

I have two different routes I will persue - one is to continue working with MIG to see if I can make that work (not yet...) and the other is to see if it's possible to pump the Rick Huang interface (which I have working flawlessly) up to 133 MHz. Since I already use dual rank synchronizers to talk to the interface from the 50 MHz clock domain, synchronization between the 133 MHz and 50 MHz clocks is not necessary, so it should be fairly simple (at first look... I know how that goes).

JovianPyx · Posted: Mon Feb 27, 2012 6:52 pm Post subject:

I add this reply because I see this thread has ended inaccurately - and in a good way Smile

I returned my attention to a design posted elsewhere by Rick Huang which I had squirrelled away on my server. His project is an audio record/playback project using the SDRAM to store the audio samples. The code turned out to be nicely written (IMO) and I was able to strip away Rick's application from the interface to SDRAM for the Spartan-3E Starter Kit. With that interface, I was able to make echo/delay for several synthesizers. The interface runs the SDRAM at 100 MHz which while not the maximum speed (133 MHz) is more than fast enough for echo/delay and reverb.

martin200 · Joined: Apr 13, 2012 Posts: 1 Location: MM

JovianPyx · Posted: Wed Mar 18, 2015 9:53 am Post subject:

engineer · Joined: Mar 31, 2014 Posts: 11 Location: Frankfurt / Germay

Although late, and add:

I just came again across the fact that some Versions of this board appeared to have a bug in the DDR-ram. Most likely the earlier Versions like mine.

JovianPyx · Posted: Thu May 28, 2015 1:16 pm Post subject:

I may have read about other possible versions of the board. If you have one that includes the physical loopback, you could try playing with the clock.

The technique I used (replaced parts of the interface supplied in the project by Rick Huang) works at 100 MHz. Not full speed (133 MHz) but quite useful at 25 megabytes per second transfer rate. It should work with all versions.