Joined: Feb 09, 2011
|Posted: Mon Feb 17, 2014 7:38 am Post subject:
some help with complex logic circuit
This is an old project I had in mind time ago but I never managed to undestand how to complete it.
It's a old school digital delay. I want to understand how those raw digital delay work, my aim is not to clone it completely to have a digital delay, since I already have plenty of digital and analog delays here, and of course if I'd want one this would be not the best design.
I'm not interested in the analog interface, I'm interested only in the analog to digital conversion and back again, and in the control logic used to get the echo effect.
this is url of the schematic (from which I removed the useless parts):
So far, what I know is:
A/D IN (top left of schematic) = analog signal (already filtered/pre-amplified) input
VCO (left, bottom) = variable voltage, ranging from 2V DC minimum to 4V DC maximum (frequency range 0.1hZ to 15hZ)
PC0 (left, center) = a simple bit coming from a uC
PA0-7 & PB0-1 (bottom) = 10 bits coming from a uC
D/A OUT (right, top) = analog signal output
My "theory of operation" is:
- The heart of the system is the 74LS624 chip, this one is the clock source for the AD and DA conversion. The frequency of this chip (provided the VCO input described above) would go from a minimum of 40khZ and a maximum of 78khZ when the VCO is oscillating. When the VCO is not oscillating, the chip would provide 64kHZ as clock.
- The AD conversion is achieved using a 12bit SAR (AM2504) + 12bit DAC (AM6012)
- The DA conversion is achieved using another AM6012
- The result of conversion (12 bit, parallel output) is stored in 12 DRAM chips, each one 64k x1 bit, so every bit of conversion got it's own DRAM chip. That means that the addressing is the same for every chip.
- The whole logic circuit used to manage DRAM storage seems to takes as input that 10 bits that I was talking above.
Those 10 bits are coming from a uC connected to knobs and display that let you choose the "echo time". I don't know the firmware contained in it, but this is what I thought:
since those are 10 bits, they can do 1024 possible values. The echo time we can get (according to datasheet) is 0 milliseconds to 1023 milliseconds with 1millisecond increment. Since the DRAM is 64k bit, and the clock frequency is 64khZ in normal conditions, I think we can assume that those 10 bits indeed specify the echo time, and so are not variable until the user change it to another echo time. So that control circuit is used to convert this number into a useful address for DRAM storage.
Then there's a 13th DRAM chip, but I don't know what is storing. To me it looks like it's storing the condition of flip-flop on the analogh path.
Are my thought corrects in your opinion?