Yusynth Clock Divider External Reset Issue

[helix_modular]

Hi everybody,

I've developed a stripboard version of this handy module and the basic functions are running smoothly.

For original design, schematic and so forth, refer to:
http://yusynth.net/Modular/EN/DIVIDER/index.html

There's a reset circuit which takes an external signal and produces a short trigger to reset all three counters -- however, this occurs on the falling flank of the reset input gate/trigger/whatever. I want the pulse to happen on the rising flank instead (and I reckon that this would be considered as 'proper' behavior of such a feature).

Any suggestions on how to fix that without changing too much of the original circuit?

(This behavior is supported by simulation, too. I've replaced the NPN Q11 with a PNP -- and this somehow 'works' but is hardly good practice due to somewhat ambiguous levels rather than 0 and 15V)

Greetings,
helix

EDIT: set description to '[SOLVED]'.

[PHOBoS]

a PNP transistor is a step in the right direction, but also connect R42 to +Vcc instead of GND.
You might have to add a resistor in series with the base of Q11 as well. It does make some
sense to have it reset on the high-to-low transition but I always use low-to-high myself.

[helix_modular]

Ace, PHOBoS!

Simulation is affirmative. Apparently I don't even have to modify the values... I'll try it out asap irl and report back.

All the best,
helix

[helix_modular]

Thanks again PHOBoS. It works exactly as you suggested.

This is what I've done:
1) Replaced Q11 with an PNP (BC557C)
2) Rotated Q11 by 180° (i.e. swap emitter and collector)
3) Connected the centre pin of Q11 (base) with R42 (22k) to Vcc+
4) Done

I've uploaded my stripboard design to this thread:
http://electro-music.com/forum/topic-69935.html

Cheers,
helix

[PHOBoS]

good to hear it works