A FlipFlop is a two-state switching device widly used in computers for storage, arithmetic and logic operations. The commonest type is bistable - effectively two linked switches, one on and one off. When 'flipped' by a trigger it switches to the opposite stable condition until 'flopped' back again. - Tristram Cary - Illustrated Compendium of Musical Technology - London 1992

Can anyone tell me how to make flipflops?

Three different types of flipflops and a way to prevent retriggering until the envelope has gone through all of the A, D, S and R stages:

Toggle ON/OFF state on alternately pressing C4. Handy to start or stop a sequence by pressing the same key.

Set-Reset type, C4 sets and D4 resets, pulse modules on the input are used to minimize the chance of Set and Reset inputs being on at the same time (disallowed state). Handy to start a sequence by a key and stop it by some other key, maybe used to start another sequence.

D-Type with reset, C4 samples and holds the inputs state (could be a blue signal as well) D4 forces the output to OFF or 0 regardless of the current outputstate. Handy to conditionally start a sequence and being able to force it to stop it by another key.

Prevents retriggering (C4) of the envelope until it's completely finished and the release state has completely faded out. Can be handy in some cases as well, e.g. if a sequence is started by the same key as well, and the envelope is a long one laid down over the whole sequence, this prevent the sequence to be accidentally restarted until it is completely finished, a sort of a one shot mode for a sequence.

Here's an example of how you can use the fourth example, press a key and a sequence will start in rhythm with the clock and you cannot do anything anymore for exactly 70 seconds (18+18+10+24sec of the release stage), whereafter you can trigger it again. Sort of a mix automation.

Here's my take on it. The low pitch represents a logical 0, and the high pitch a logical 1. When the clock is high, the output Q echos the input "Data D" (hence the name D-flipflop) and the output Not Q echos the negated value of D. When the clock is low, the flipflop is "stable".

As far as I can tell this works 100%.. it seems to remember the last input values when its in a stable state. I have no idea what to use this patch for though.. I just made it and thought "Hmm.. neat."

To do flip-flop things I use a sequencer module with steps set to 2 and setp1 having value 0 and step2 value 64. Each gate signal then toggles between the two steps/states.

Here is my solution to this. Using a sequencer module would be working and even simpler... But I spent so much time in inventing (re-inventing, I suppose) that I must show you...

You can also use a ClockDivider module with the divider value set to 2.