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 Forum index » DIY Hardware and Software » Microcontrollers and Programmable Logic
I2S Input Verilog Code Anywhere?
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skrasms



Joined: Feb 21, 2008
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Location: Portland, OR
PostPosted: Sat May 02, 2009 1:44 pm    Post subject: I2S Input Verilog Code Anywhere? Reply with quote  Mark this post and the followings unread
I'm looking for an I2S input interface for an FPGA. Opencores.org has one, but I have yet to make it through their screening process.

Is that something anyone has handy?
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skrasms



Joined: Feb 21, 2008
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Location: Portland, OR
PostPosted: Sat May 02, 2009 4:39 pm    Post subject: Reply with quote  Mark this post and the followings unread
Scratch that; opencores let me make an account Smile
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State Machine
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PostPosted: Wed Jun 17, 2009 9:19 am    Post subject: Reply with quote  Mark this post and the followings unread
Quote:
I'm looking for an I2S input interface for an FPGA. Opencores.org has one, but I have yet to make it through their screening process.

Is that something anyone has handy?


There are I2S interfaces (MASTER/SLAVE Units) on "opencores" but are VHDL based and incorporate the Wishbone interface standard so you may want to become familiar with that standard so do take a peek at the document they have posted there. It's a 150 page document ... Shocked

Bill
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skrasms



Joined: Feb 21, 2008
Posts: 121
Location: Portland, OR
PostPosted: Sun Jun 21, 2009 7:08 pm    Post subject: Reply with quote  Mark this post and the followings unread
State Machine wrote:
Quote:
I'm looking for an I2S input interface for an FPGA. Opencores.org has one, but I have yet to make it through their screening process.

Is that something anyone has handy?


There are I2S interfaces (MASTER/SLAVE Units) on "opencores" but are VHDL based and incorporate the Wishbone interface standard so you may want to become familiar with that standard so do take a peek at the document they have posted there. It's a 150 page document ... :shock:

Bill


Thanks for the heads up!

After I looked at the code on opencores and found out I needed to use a whole new interface standard to make it work, I put this on the back burner. It's nice and warm, but won't be cooking for a while.
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State Machine
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PostPosted: Mon Jun 22, 2009 11:02 am    Post subject: Reply with quote  Mark this post and the followings unread
Quote:
Thanks for the heads up!

After I looked at the code on opencores and found out I needed to use a whole new interface standard to make it work, I put this on the back burner. It's nice and warm, but won't be cooking for a while.


Your very welcome. Wink I grabbed the Wishbone document myself just to take a peek at the interface standard just to get a headstart. Seems open ended enough and supports both single, variable word width, transfers and block transfers with handshaking & Interrupt Logic. Kind of reminds me of a VME bus in a way.

It might be a good thing to adopt a standard SOC interconnection standard , such as Wishbone, at some point here on this subforum so that all us forum members can eventually share IP much more easily. Much like opencores does. opensynthcores if you will Wink

Bill
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