R/2R - Me Heartys - Yo Ho Ho

[Uncle Krunkus]

I take it that the deathly silence on this idea means: -
a) Someone has called the nuthouse and it just takes a while for them to arrive.
b) Nobody understands what I'm going on about.
or
c) Giving a nice cosy home to so many CMOS cockroaches is not generally supported/encouraged.

So, I'm just going to test it out and then we'll see who's "crazy" won't we?

Just wait until me and my 5 ton sub-oscillator take over the world! Won't be laughing then will we?

[blue hell]

[Uncle Krunkus]

Here it is!
It now has 5bit voltage resolution and 16 timeslices. Samples 9-16 are 1-8, in reverse order, inverted, and dropped into the -ve side of the wave.
I'm pretty impressed with this so far. The sample is recorded from the breadboarded version. I still haven't added any de-coupling caps, and it already sounds pretty smooth.

In the sample we have about 3sec each of: -
1. All counters slow
2. 1 up/down fast
3. 2 up/down fast
4. 4 up/down fast
5. 1 up fast
6. All fast
And then the clock is turned down at the end.

I've also included the schem as it is on the breadboard. (counters not shown)

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[Uncle Krunkus]

I found out last night that all my counters, (there are 8 of them) were sometimes miss-clocking, which meant 1, 2, or 3 counts were being skipped over because of noisy clocks. A 100nF bypass cap added to the back of each 556 has cleaned everything up. This does make a big difference, as skipping counts causes a lot more jarring in the timbre morphing. I'm going to change all of them to up/down counters as well, becuse the up only ones suffer the same problem of inducing a big shift in the harmonic content when they reset to 0000. If I want the sudden change, I can get it back later with the addition of triggered "resets".

[crazeydazey]

that's a scary avatar change there uncle K...

[Uncle Krunkus]

Yeah, well, I'm a scary kinda guy!

This is actually Maria's half cousin Boris. He's animated through the use of a power other than electricity. The power of beer!
At a birthday party a few years ago, after about 15 of said beers, it was deemed that Boris would look better if he put his mask back on!
This picture was taken about 5 mins later.

[richardc64]

I don't see why you need the 4050s. There's no level translation, since everything runs off 12V, and the output low and high voltages are the same as the 4030s. Buffer the MSB with a left over 4081 and you can eliminate one chip.

Or am I missing something?

[Uncle Krunkus]

No, you're right, I don't really need them. They were there before the XORs showed up, and I left them there to keep all the bits coming off the same chip.

[Uncle Krunkus]

The problem is that I'm gonna lose the 4081 anyway. I need a set of NANDs to build a little flip-flop, and the other two are to re-create the AND on the 4017s. Then I'm gonna need the 4050 to buffer the MSB.
But that could all change before anything gets set in stone.

Hey,... The flip-flop is gonna supply the MSB, so that won't need buffering anymore will it? Thanks for getting me thinking about that Richard.

[Uncle Krunkus]

It seems now that I'm going to need a separate Flip-flop chip. Now that is going to drive the MSB and sit across the XORs. So I assume it wil need buffering on the MSB line.
If I continued to use a 4081 for the AND gate on the 4017s, I could just tie one of the ANDs up as my MSB buffer yeah?
This way, I at least get rid of the buffer chip (4050).

BTW this is exactly what Richard said in the first place! Man! I think I'm missing something!

[richardc64]

[Uncle Krunkus]

Here's the latest schem. It's working very well. On breadboard. Once I've sussed the PLL front end I'll put both on a stripboard.

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[Uncle Krunkus]

I want to drive this DAC with a clock derived from a frequency multiplier based on Scott Gravenhorsts PLL design for the FatMan, which can be found here: - http://home1.gte.net/res0658s/fatman/4046pll.html

I'm not sure how to deal with the fact that his design references everything off -V though. It would mean that the output would be a series of negative going pulses, and this circuit I've been playing with triggers off positive going pulses. Of course I could put an inverter/buffer in there, but could I just bump the reference up to the 0V line instead? Did he do that just because it's for the FatMan?

[blue hell]

[Uncle Krunkus]

No, I won't be using the pots. Just a rotary to choose which multiplier.

[Uncle Krunkus]

Here's the schem I'm going to use to build up this output section on stripboard. I think.
Have a look at the bottom right hand corner. Does that little 10R*2 and a 1uF make for a good digital filter. Can anyone see any problems with it?
Also, the AGnd which goes to pin3 on the TL071, if I put a divider on that, could I use it to centre the wave around 0V?

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[fonik]

i am totaly lost! all that logic. could you explain in plain words what that circuit actually does? what are the data inputs 1-4 are fed with?

[Uncle Krunkus]

This is about as simple as I can explain it.
Step A through H (from the 4017s) simply scans back and forth sequentially strobing 8 * 4bit counter outputs. As the counter is strobed, it's output (4bits) is applied to the data inputs (1 to 4). The 5th data line is a trick which goes high on the way back and effectively creates a 5 bit DAC with only 4 bit inputs. This data is also inverted by the XORs so that the trough is a mirror of the peak (but backwards ).
Of course whether it is inverted or not can be controlled, as this makes a big difference to the harmonic structure. Also, the point where the 5th bit shifts everthing into -ve territory can be controlled with S1 which acts as a strange kind of Pulse Width control.
Does that make sense?
It's an absolute CMOS roach condo, but is proving to be a lot of fun, and has taught me heaps.

[fonik]

thank you very much, uncle k.

so the counter is not part of the schematic!?
and the clock actually sets the frequency of this oscil... err... DACillator?

(sorry for being dense)

[Uncle Krunkus]

Well, the 8 * 4bit counters are on other schems/boards yes.
And the clock, as it arrives on this board, needs to be 2, 3, 4 octaves above the fundamental of this circuit's output. (as it is divided by 16 as part of the DAC/strobing process). I plan on building a front end which uses a PLL and divider to bump it up by say 3 octaves first.

[fonik]

very nice, mon oncle...
i just started to build a 3rd cabinet (despite any contrary decisions i made). so i will have enough space for that dacillator coming.

[Uncle Krunkus]

I'm very flattered Fonik,
you're the only person who has shown any interest in actually building this little "distraction" so far!
If you think there's a lot of logic on this board, you should see the counter boards! It's definitely not for the faint hearted! And keep in mind that I can't gaurantee that it will produce something which justifies the amount of work involved. Still, it's nice to know that someone's watching over me.
Have a listen to the sound samples I've posted so far, they're not anything to write home about at this stage, but I'm happy with the progress.
What do you think of the digital power rail filter?

[State Machine]

[richardc64]

[Uncle Krunkus]