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Cynosure
Site Admin
Joined: Dec 11, 2010 Posts: 966 Location: Toronto, Ontario - Canada
Audio files: 82
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Posted: Sat Jan 20, 2018 9:35 pm Post subject:
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Phobos - wouldn't a couple of long shift registers work too? Adjust the clock speed to change the delay.
Kind of like this thing, but with only one tap at the end: http://electro-music.com/forum/topic-57022.html
Your 4093 circuit is over my head _________________ JacobWatters.com |
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PHOBoS
Joined: Jan 14, 2010 Posts: 5591 Location: Moon Base
Audio files: 705
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Posted: Sun Jan 21, 2018 8:18 am Post subject:
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Cynosure wrote: | Phobos - wouldn't a couple of long shift registers work too? Adjust the clock speed to change the delay. |
A shiftregister initally came to mind too, see my first reply:
PHOBoS wrote: | something with a shiftregister ? clk sets delay time, but you would need a flip flop or something at the data input if the pulse
is shorter then a CLK cycle. You could use some logic to control the time digitally too by setting the number of places it shifts.
(a mux that selects where you take the pulse out) |
In theory if you have a looooong shiftregister and a pretty fast clock than what you put in you get out but delayed. As I mentioned
that would also make it possible to control the delay time with a digital signal. There are a couple of problems though, the main one
being resolution. If the pulse length is a lot shorter than the delay time the shiftregister needs to be very long. For example with a
100mS pulse and a 10 second delay you'd need 100 steps. But it gets much worse if the pulse length is not a nice division of the delay
time. If you would want a 105mS pulse length you already need 2000 steps. There is a solution to this which is to add a monostable
circuit at the end which would take a pulse input and convert is into a gate signal with adjustable length. However, if you do that you
no longer need the shiftregister and could just use a simple counter.
Another problem is the length of the input pulse. If it is very short you'd need a very fast clock which also results in a lot of steps
or it could fall between the CLK cycles and nothing would happen. The solution to this is to add another monostable circuit at the input
or a flip-flop (astable) to 'capture' the input pulse. So a monostable circuit or flip-flop followed by a counter or shiftregister followed
by another monostable circuit would do the trick and that is basically what the 4093 circuit is.
I am not sure why it is over your head, do you recognise U1c & U1d as a flip-flop ? (U1a & U1b are used as inverters) Keep in mind that
the circuit does not simply delay a pulse as you would with a standard delay. The length of the output pulse is (almost) independent from
the length of the input pulse. As soon as it detects a low to high transition it springs into action and after a certain (adjustable) delay time
it will give an ouput pulse that has an adjustable length. You could see it as a 3 step counter (0,1,2):
- 0 is the initial state before anything happens.
- When there is a low to high transition it will go to step 1.
- After the delay time has passed it will go to step 2 and the output becomes high.
- After the gate length time has passed it will reset itself and return to 0 and the output becomes low again. (unless the input is still high) _________________ "My perf, it's full of holes!"
http://phobos.000space.com/
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Estebandito
Joined: Dec 25, 2017 Posts: 30 Location: Amsterdam
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Posted: Thu Jan 27, 2022 7:30 am Post subject:
Re: PHOBoS - Pulse Delay schematic Subject description: 1 NAND to delay them all |
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PHOBoS wrote: |
If the pulse input is still high after the cycle ends the pulse out will also stay high untill the input becomes low again. |
With regards to this; what happens if -after triggering the cycle- the input goes low first and then high again before the cycle has finished? Will that input be ignored? I am asking because I am looking for such a circuit (4xxx or 555 based) but I can't find one. |
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PHOBoS
Joined: Jan 14, 2010 Posts: 5591 Location: Moon Base
Audio files: 705
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Posted: Thu Jan 27, 2022 8:54 am Post subject:
Re: PHOBoS - Pulse Delay schematic Subject description: 1 NAND to delay them all |
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Estebandito wrote: | With regards to this; what happens if -after triggering the cycle- the input goes low first and then high again before the cycle has finished? Will that input be ignored? |
yes, any pulses that happen before the cycle is finished wil be ignored. This is because of the flipflop at the input made with U1c and U1d.
The first pulse will set this flipflop and only at the very end of the cycle will it get reset, so any pulses that happen before that time would
set it but since it's already set that doesn't make any difference. _________________ "My perf, it's full of holes!"
http://phobos.000space.com/
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Estebandito
Joined: Dec 25, 2017 Posts: 30 Location: Amsterdam
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Posted: Fri Jan 28, 2022 3:34 am Post subject:
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Thanks, that is perfect; exactly what I was looking for |
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