Question about CPLDs

skrasms · Joined: Feb 21, 2008 Posts: 121 Location: Portland, OR

I am familiar with PAL chips from my college digital logic days, but they had a lot of limitations. Right now I am looking for a chip that I can use in a pretty complicated scheme, and I wonder if it is possible with a CPLD.

I need a programmable logic chip that I can make into two halves sharing information. One half interfaces with a processor running about 2 MHz, and the other interfaces with a processor running at around 80MHz.

The point of this chip would be to take timing burdens away from the processor running at 80MHz. The 2MHz processor needs *new* data (not just old data repeated) on every clock cycle, so whatever is running on the 80MHz processor has to be interrupted for a data output routine. It makes any other code execute very slowly because of all the data output routine calls.

So I am hoping I can get some kind of programmable logic chip into this system that will guarantee the 2MHz processor is always getting the right data at the right time, and also that the 80MHz processor doesn't need to be concerned with what the 2MHz processor is doing.

Sometimes the 80MHz chip will have too much data to give the 2MHz chip at once, so it will need to get queued. Other times the 2MHz chip will need data while the 80MHz chip is doing other calculations, so then this "middle-man" chip can make sure it gets some data to keep it happy.

Right now I have everything working with no middle-man CPLD, but the queue and interrupt routines are just bogging down the 80MHz processor way too much. Also, I'm using a lot of glue logic chips in between processors that I could easily save with a single PAL chip.

Does that sound like something a CPLD could handle? It seems like something I could create on a simple PAL with the exception of the queue system that I need.

urbanscallywag · Joined: Nov 30, 2007 Posts: 317 Location: sometimes

You won't have a lot of memory in a CPLD to buffer the data going in between the two processors. Depending on how much you need you could either interface the CPLD to some SRAM or move into an FPGA which may have enough RAM on board. The disadvantage with FPGA is that you'll need some FLASH to configure at startup, the advantage is you may be able to put more or all of your project onto an FPGA (including processors).

skrasms · Joined: Feb 21, 2008 Posts: 121 Location: Portland, OR

urbanscallywag · Joined: Nov 30, 2007 Posts: 317 Location: sometimes

I see. 16-bytes sounds entirely reasonable, 16*8 = 128 flip flops. You'll need some more for whatever state machine or FIFO controller you implement. So a CPLD with 192 flip flops in a TQFP-100 looks like $6 in quantity 1. I think that should suit your needs.

skrasms · Joined: Feb 21, 2008 Posts: 121 Location: Portland, OR

urbanscallywag · Joined: Nov 30, 2007 Posts: 317 Location: sometimes

I don't know about 16V8 but for CPLD or FPGA there are parallel -> JTAG programming cables that are reasonably priced. You might even be able to DIY one. Smile