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 Forum index » DIY Hardware and Software » Circuit Bending
using negative regulator to pull up ground?
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noto



Joined: Nov 05, 2009
Posts: 23
Location: portland

PostPosted: Mon Jan 23, 2017 9:19 am    Post subject: using negative regulator to pull up ground? Reply with quote  Mark this post and the followings unread

hello! i was wondering if anyone could offer some guidance. i am working with a single supply(batteries), and i need to create a regulated 5 volt supply for a few TTL chips, comparator based clock oscillators, and some capacitve touch sensors. but rather than regulating down from the positive supply with say the 7805, would it be ok to regulate up from negative supply using the 7905? i am trying to isolate the 0v supply of the unregulated stuff from the 0v supply to the 5 volt stuff... it seems like it makes sense, but i feel like i might be missing something. maybe something to do with N/P junctions.... any advice?


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JovianPyx



Joined: Nov 20, 2007
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PostPosted: Mon Jan 23, 2017 10:11 am    Post subject: Reply with quote  Mark this post and the followings unread

Pin 3 will be 5 volts lower than pin 1. That means that pin 3 will be (V+ - 5).

So if V+ is 9 volts, you'll see pin1 at 9v and pin 3 at 4v. Inputs to the TTL gates must be referenced to pin 1 (or V+).

Whether that is useful depends on the rest of your circuit.

The TTL gates will have output states at V+ and V+ - 5.

Curious - why use TTL? TTL draws a lot of current compared to CMOS gates. CMOS also tolerates a wide range of voltages from 3 to 15.

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noto



Joined: Nov 05, 2009
Posts: 23
Location: portland

PostPosted: Mon Jan 23, 2017 11:29 am    Post subject: Reply with quote  Mark this post and the followings unread

hello! thanks for the quick response. i guess TTL was the wrong term. i really just meant "digital" voltage range. anyway, i have breadboarded the circuit and i am definitely getting 5 volts across pin1 and pin3. i am probably just overthinking this... the other part of my circuit is a CD4051 analog multiplexer. the goal is to isolate the VSS and VEE rails from each other. i have an LFO that is driving a counter chip for the multiplexer, and it is causing some "warble" in a sample and hold chip down the line. i basically just want to know if this is an "ok" way to use a negative voltage regulator.
thanks in advance Smile


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JovianPyx



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PostPosted: Mon Jan 23, 2017 11:38 am    Post subject: Reply with quote  Mark this post and the followings unread

I don't see a problem with using a negative voltage regulator.

What is important will be that the CMOS chips will have logic inputs that are referenced to the Vss pin.

I doubt that the warble is coming the regulator, but you'll want to use an oscope on the power rails of the chip that's warbling and ensure that it's rails are stable.

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noto



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PostPosted: Mon Jan 23, 2017 11:47 am    Post subject: Reply with quote  Mark this post and the followings unread

thanks!
yeah, i think i could probably just clean up the supply.
the regulator idea just sparked my curiosity. still have a lot to learn...
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