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samsam
Joined: Mar 01, 2017 Posts: 22 Location: France
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Posted: Sat Mar 04, 2017 11:53 am Post subject:
cd40106 jumping in tones |
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Hi everyone.
I'm building something that should be really easy.
I have two oscillators made out of a cd40106 chip. Problem is that the sweep is not smooth between notes when i turn my 100k potentiometer. I have tried many different capacitor but the result still the same. My oscillator is jumping from note to note.
Do you have any idea of what may be causing this ? |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Sat Mar 04, 2017 12:16 pm Post subject:
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If the 100K pot isn't new, there could be worn spots on the resistive element which will definitely cause this exact symptom.
Ever turn a volume knob on an old amp and have the sound crackle or jump? Same issue.
I can't think of anything else other than that. Even if the pot is brand new, I'd try another new one. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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blue hell
Site Admin
Joined: Apr 03, 2004 Posts: 24079 Location: The Netherlands, Enschede
Audio files: 278
G2 patch files: 320
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Posted: Sat Mar 04, 2017 12:34 pm Post subject:
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two oscillators on one chip? if so - they may sync to each other. could try to decouple the power supply (capacitor over it close to the chip). _________________ Jan
also .. could someone please turn down the thermostat a bit.
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Sat Mar 04, 2017 1:04 pm Post subject:
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Blue Hell wrote: | two oscillators on one chip? if so - they may sync to each other. could try to decouple the power supply (capacitor over it close to the chip). |
Oh yes, that's possible too. However, bypassing may not completely eliminate the problem because the gates are tied together internally which means that each oscillator cannot be separately bypassed. A better way is to use 2 chips, one for each oscillator, power each chip through an LED from V+ to the Vdd pin and a cap (like 100uF) from Vdd to ground. That is the way it's done in the PAiA Fatman and it works very well. Do not expect the LED to light, the 40106 won't draw enough current for that, however, the LED will work as a light weight diode regardless of whether it lights or not. A small signal diode such as 1N4148 will not work (at least it's never worked for me). _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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samsam
Joined: Mar 01, 2017 Posts: 22 Location: France
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Posted: Sat Mar 04, 2017 2:43 pm Post subject:
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Thanks for the replies.
I have tried with one oscillator only and it does the same thing. Same problem when i change the pot, it jumps from note to note.
I have changed the 5 volt power supply for a 9 volt and it seems to work ok know.
Does this chip doesn't work on 5 volt ? |
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PHOBoS
Joined: Jan 14, 2010 Posts: 5591 Location: Moon Base
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Sat Mar 04, 2017 8:34 pm Post subject:
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What PHOBoS said...
and
Can you show us the *exact* schematic? _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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samsam
Joined: Mar 01, 2017 Posts: 22 Location: France
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Posted: Sun Mar 05, 2017 7:19 am Post subject:
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I didn't know all the other inputs of the chips had to be connected as well.
Should they be connected to ground ?
the schematic is really the most basic way to make oscillators out of a cd40106.
Pin 14 to ground
Pin 7 to 5 or 9 volt
Pin 1 with a capacitor to ground
A 100k potentiometer connected between pin 1 and 2. |
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JovianPyx
Joined: Nov 20, 2007 Posts: 1988 Location: West Red Spot, Jupiter
Audio files: 224
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Posted: Sun Mar 05, 2017 8:23 am Post subject:
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In all cases of CMOS logic devices, unused inputs must be grounded (Vss) or tied to Vdd. Unused outputs should be left open.
Given that we're talking about an unused logic gate, it makes no difference whether the inputs are tied high or low. Do as is convenient for the layout. Just never leave them open. _________________ FPGA, dsPIC and Fatman Synth Stuff
Time flies like a banana. Fruit flies when you're having fun. BTW, Do these genes make my ass look fat? corruptio optimi pessima
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