Power on Reset for digital U5

[elmegil]

I had a Klee that I'd built that wouldn't let you clock it on first startup, until after you hit the load button one time. So I could have it patched up with a clock to the clock in, the clock enable on, power on the case, it would load some bits into the pattern on startup, but they'd stay where they were even though the master clock & gate bus LEDs were clearly clocking.

I found that Q1 on U5 (pin 1) was staying high at first power on. This holds the CD4034's in Parallel load mode, so the serial clocking doesn't have any effect.

I did some figuring about what values to use for a power on reset (POR) circuit for U5, and anded up with 10uF, 5.1K, and 15K. Works nicely, and the module clocks immediately on power up now.

Pin 4 is pin 4 of U5, which is the reset for the first flip flop. The 5.1K is to isolate the cap to the +rail from U4 during normal operation, since resetting the flip flop is part of how the load works.

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